Maxq610 user’s guide – Maxim Integrated MAXQ610 User Manual

Page 68

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MAXQ610 User’s Guide

DESCRIPTION

WDCN, 08h[0Fh]

Watchdog Control Register (8 bits)

Initialization

Bits 5, 4, 3, and 0 are cleared to 0 on all forms of reset; for others, see individual bit
descriptions .

Access

Unrestricted direct read/write access .

WDCN.0 (RWT)

Reset Watchdog Timer. Setting this bit to 1 resets the watchdog timer count . If watchdog
interrupt and/or reset modes are enabled, the software must set this bit to 1 before the
watchdog timer elapses to prevent an interrupt or reset from occurring .
This bit always returns 0 when read .

WDCN.1 (EWT)

Enable Watchdog Timer Reset. If this bit is set to 1 when the watchdog timer elapses,
the watchdog resets the processor 512 system clock cycles later unless action is taken to
disable the reset event . Clearing this bit to 0 prevents a watchdog reset from occurring but
does not stop the watchdog timer or prevent watchdog interrupts from occurring if EWDI
= 1 . If EWT = 0 and EWDI = 0, the watchdog timer is stopped . If the watchdog timer is
stopped (EWT = 0 and EWDI = 0), setting the EWT bit resets the watchdog interval and
resets counter, and enables the watchdog timer .
This bit is cleared on power-fail and power-on reset and is unaffected by other forms of
reset .

WDCN.2 (WTRF)

Watchdog Timer Reset Flag. This bit is set to 1 when the watchdog resets the processor .
Software can check this bit following a reset to determine if the watchdog was the source
of the reset .
Setting this bit to 1 in software does not cause a watchdog reset . This bit is cleared by
power-fail and power-on reset only and is unaffected by other forms of reset . It should also
be cleared by software following any reset so that the source of the next reset can be cor-
rectly determined by software .
This bit is only set to 1 when a watchdog reset actually occurs, so if EWT is cleared to 0
when the watchdog timer elapses, this bit is not set .

WDCN.3 (WDIF)

Watchdog Interrupt Flag. This bit is set to 1 when the watchdog timer interval has
elapsed or can be set to 1 by user software . When WDIF = 1, an interrupt request occurs
if the watchdog interrupt has been enabled (EWDI = 1) and not otherwise masked or
prevented by a higher priority interrupt already in service (i .e ., IGE = 1, and IPS = 11b
or lower priority interrupt in service in order for the interrupt to occur) . This bit should be
cleared by software before exiting the interrupt service routine to avoid repeated inter-
rupts . Furthermore, if the watchdog reset has been enabled (EWT = 1), a reset is sched-
uled to occur 512 system clock cycles following setting of the WDIF bit .

WDCN.4 (WD0)
WDCN.5 (WD1)

Watchdog Timer Mode Select Bit 0
Watchdog Timer Mode Select Bit 1. These bits determine the watchdog interval or the
length of time between resetting of watchdog timer and the watchdog generated interrupt
in terms of system clocks . Modifying the watchdog interval through the WD[1:0] bits auto-
matically resets the watchdog timer unless the 512 system clock reset counter is already in
progress, in which case, changing the WD[1:0] bits does not affect the watchdog timer or
reset counter .

WD1

WD0

CLOCKS UNTIL

INTERRUPT

CLOCKS UNTIL RESET

+ 512