Maxim Integrated MAXQ610 - Manual (Page 119)

8-6
MAXQ610 User’s Guide
On the first qualified event, it does the following:
1) Captures the IRRX pin state and transfers its value to IRDATA . If a falling edge occurs, IRDATA = 0 . If a rising edge
occurs, IRDATA = 1 .
2) Transfers its current IRV value to the IRMT .
3) Resets IRV content to 0000h (if IRXRL = 1) .
4) Continues counting again until the next qualified event .
If the IR timer value rolls over from 0FFFFh to 0000h before a qualified event happens, the IR timer overflow (IROV)
flag is set to 1 and an interrupt is generated, if enabled . The IR module continues to operate in receive mode until it is
stopped by switching into transmit mode (IRMODE = 1) or clearing IREN = 0 .
8.5 Carrier Burst-Count Mode
A special mode has been implemented to reduce the CPU processing burden when performing IR learning functions .
Typically, when operating in an IR learning capacity, some number of carrier cycles is examined for frequency determi-
nation . Once the frequency has been satisfactorily determined, the IR receive function can be reduced to counting the
number of carrier pulses in the burst and the duration of the combined mark-space time within the burst . To simplify this
process, the receive burst-count mode (as enabled by the RXBCNT bit) can be used . When RXBCNT = 0, the standard
IR receive capture functionality is in place . When RXBCNT = 1, the IRV capture operation is disabled and the interrupt
flag associated with the capture no longer denotes a capture . In the carrier burst-count mode, the IRMT register is
now used only to count qualified edges . The IRIF interrupt flag (normally used to signal a capture when RXBCNT = 0)
now becomes set if ever two IRCA cycles elapse without getting a qualified edge . The IRIF interrupt flag thus denotes
absence of the carrier and the beginning of a space in the receive signal . When the RXBCNT bit is changed from 0 to
1, the IRMT register is set to 0001h . The IRCFME bit is still used to define whether the IRV register is counting IRCLKs
or IRCA-defined carrier cycles . The IRXRL bit is still used to define whether the IRV register is reloaded with 0000h on
detection of a qualified edge (per the IRXSEL[1:0] bits) .
Figure 8-6 and the descriptive sequence embedded in the figure illustrate the expected usage of the receive burst-
count mode .
8.6 IRV Stand-Alone Count Mode
A special mode has been implemented to allow using the IRV as a simple counter . When IRVCEN = 1 and IRMODE
= 0, the IRV acts as an up counter counting IRCLK edges (IRCFME = 1) or carrier-generated clock edges (IRCFME =
0) . If IREN = 1 and IRXRL = 1, a qualifying edge resets the IRV counter and generates an interrupt (if enabled) . Using
this feature when IREN = 0 allows controlling the IRTX pin with the PWCN IRTX control bits .
This mode should not be used with RXBCNT set and is not operational if IRMODE = 1 .