Maxim Integrated MAXQ610 - Manual (Page 61)

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MAXQ610 User’s Guide
REGISTER DESCRIPTION
PRIV, 08h[02h] Privilege Register (8 bits)
Initialization This register is reset to 00001111b on all resets .
Bits 3 and 2 are cleared by hardware when the current IP is not in utility ROM code, nor
system code .
Bits 1 and 0 are cleared by hardware when the current IP is not in utility ROM, system, nor
user loader code .
Access Bits 3 and 2 can only be modified by utility ROM code, or system code . Bits 1 and 0 can
only be modified by utility ROM code, system code, or user loader code . Unrestricted read
access .
Writing this register clears the PRIVT0 register .
PRIV.0 (PULR) User Loader Read Privilege. This bit defaults to 1 on a power-on reset . When this bit
is 1, code can read the user loader memory area . Clearing this bit to 0 disables reading
from user loader memory and any read attempt generates a protection-fault interrupt . Note
that this bit is automatically cleared when the current IP is not in utility ROM code, system
memory, or user loader memory .
PRIV.1 (PULW) User Loader Write Privilege. This bit defaults to 1 on a power-on reset . This bit defaults
to 1 on a power-on reset . When this bit is 1, code can write (program) the user loader
memory area . Clearing this bit to 0 disables writing to user loader memory and any write
attempt generates a protection-fault interrupt . Note that this bit is automatically cleared
when the current IP is not in utility ROM code, system memory, or user loader memory .
PRIV.2 (PSYR) System Read Privilege. This bit defaults to 1 on a power-on reset . When this bit is 1, code
can read the system memory area . Clearing this bit to 0 disables reading from system
memory and any read attempt generates a protection-fault interrupt . Note that this bit is
automatically cleared when the current IP is not in utility ROM code or system memory .
PRIV.3 (PSYW) System Write Privilege. This bit defaults to 1 on a power-on reset . This bit defaults to 1 on
a power-on reset . When this bit is 1, code can write (program) the system memory area .
Clearing this bit to 0 disables writing to system memory and any write attempt generates
a protection-fault interrupt . Note that this bit is automatically cleared when the current IP is
not in utility ROM code or system memory .
PRIV.7 to PRIV.4 Reserved . Reads return 0 .
PRIVT0, 08h[03h] Privilege Register Atomic 0 (8 bits)
Initialization This register is reset to 00h on all resets, and on any write to the PRIV register, or the
PRIVT1 destination .
Bits 3 and 2 are cleared by hardware when the current IP is not in utility ROM code, nor
system code .
Bits 1 and 0 are cleared by hardware when the current IP is not in utility ROM, system, nor
user loader code .
Access Bits 3 and 2 can only be modified by utility ROM code, or system code . Bits 1 and 0 can
only be modified by utility ROM code, system code, or user loader code . Unrestricted read
access .
PRIVT0.3 to PRIVT0.0 Privilege Atomic 0 Bits. These bits default to 0 on a power-on reset . The bits are used as
a logical AND bit mask when writing to PRIVT1 .
PRIVT0.7 to PRIVT0.4 Reserved . Reads return 0 .