3 breakpoint 5 register (bp5), 4 using breakpoints, Maxq610 user’s guide – Maxim Integrated MAXQ610 User Manual

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MAXQ610 User’s Guide

user program . If an address match is detected, a break occurs, allowing the debug engine to take over control of the
CPU and enter debug mode .
When (REGE = 1): This register serves as one of the two register breakpoints . A break occurs when the destination
register address for the executed instruction matches with the specified module and index .

12.2.3 Breakpoint 5 Register (BP5)

This register is accessible only through background mode read/write commands .
When (REGE = 0): This register serves as one of the two data memory address breakpoints . When DME is set in
background mode, the debug engine monitors the data memory address bus activity while the CPU is executing the
user program . If an address match is detected, a break occurs, allowing the debug engine to take over control of the
CPU and enter debug mode .
When (REGE = 1): This register serves as one of the two register breakpoints . A break occurs when two conditions
are met:
Condition 1: The destination register address for the executed instruction matches with the specified module and
index .
Condition 2: The bit pattern written to the destination register matches those bits specified for comparison by the
ICDD data register and ICDA mask register . Only those ICDD data bits with their corresponding ICDA mask bits are
compared . When all bits in the ICDA register are cleared, Condition 2 becomes a don’t care .

12.2.4 Using Breakpoints

All breakpoint registers (BP0 to BP5) default to the 0FFFFh state on power-on reset or when the test-logic-reset TAP
state is entered . The breakpoint registers are accessible only with background mode read/write commands issued over
the TAP communication link . The breakpoint registers are not read/write accessible to the CPU .
Setting the debug mode enable (DME) bit in the ICDC register to 1 enables all six breakpoint registers for breakpoint
match comparison . The state of the break-on register enable (REGE) bit in the ICDC register determines whether the
BP4 and BP5 breakpoints should be used as data memory address breakpoints (REGE = 0) or as register breakpoints
(REGE = 1) .
When using the register matching breakpoints, it is important to realize that debug mode operations (e .g ., read data
memory, write data memory, etc .) require use of ICDA and ICDD for passing of information between the host and
MAXQ610 microcontroller utility ROM routines . It is advised that these registers be saved and restored or be reconfig-
ured before returning to the background mode if register breakpoints are to remain enabled .
When a breakpoint match occurs, the debug engine forces a break and the MAXQ610 microcontroller enters debug
mode . If a breakpoint match occurs on an instruction that activates the PFX register, the break is held off until the
prefixed operation completes . The host can assess whether debug mode has been entered by monitoring the status
bits of the 10-bit word shifted out of the TDO pin . The status bits change from the nondebug (00b) state associated
with background mode to the debug-idle (01b) state when debug mode is entered . Debug mode can also be manually
invoked by host issuance of the debug background command .