Maxim Integrated MAXQ610 - Manual (Page 75)

5-3
MAXQ610 User’s Guide
Table 5-3. Peripheral Register Reset Values
Table 5-2. Peripheral Register Bit Function (continued)
REG
BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PO4 — — PO4[5:0]
WUTC — — — — — — WTF WTE
WUT WUT[15:0]
PI4 — — PI4[5:0]
PWCN — — — — — — PFRCK1 PFRCK0 PFRST IRRXWP IRTXOUT IRTXOE REGEN PFI PFIE PFD
PD4 — — PD4[5:0]
TB0R TB0R[15:0]
TB0CN C/TB — — TBCS TBCR TBPS2 TBPS1 TBPS0 TFB EXFB TBOE DCEN EXENB TRB ETB CP/RLB
TB1R TB1R[15:0]
TB1CN C/TB — — TBCS TBCR TBPS2 TBPS1 TBPS0 TFB EXFB TBOE DCEN EXENB TRB ETB CP/RLB
IRCN — — — IRDIV[2:0] IRENV[1:0] IRXRL IRCFME IRRXSEL[1:0] IRDATA IRTXPOL IRMODE IREN
IRCA IRCAH[7:0] IRCAL[7:0]
IRMT IRMT[15:0]
IRCNB — — — — RXBCNT IRIE IRIF IROV
TB0C TB0C[15:0]
TB0V TB0V[15:0]
TB1C TB1C[15:0]
TB1V TB1V[15:0]
IRV IRV[15:0]
SCON0 SM0/FE SM1 SM2 REN TB8 RB8 TI RI
SBUF0 SBUF0[7:0]
SCON1 SM0/FE SM1 SM2 REN TB8 RB8 TI RI
SBUF1 SBUF1[7:0]
SPIB SPIB[15:0]
SPICN STBY SPIC ROVR WCOL MODF MODFE MSTM SPIEN
PR0 PR0[15:0]
SMD0 — — — — — ESI0 SMOD0 FEDE0
PR1 PR1[15:0]
SMD1 — — — — — ESI1 SMOD1 FEDE1
SPICF ESPII SAS — — — CHR CKPHA CKPOL
SPICK CKR[7:0]
REG
BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PO0 0 0 0 0 0 0 0 0
PO1 0 0 0 0 0 0 0 0
PO2 0 0 0 0 0 0 0 0
PO3 0 0 0 0 0 0 0 0
EIF0 0 0 0 0 0 0 0 0
EIE0 0 0 0 0 0 0 0 0