Maxim Integrated MAXQ610 - Manual (Page 161)

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MAXQ610 User’s Guide
12.3.3 Single-Step Operation (Trace)
The debug engine supports single step operation in debug mode by executing a Trace command from the host . The
debug engine allows the CPU to return to its normal program execution for one cycle and then forces a debug mode
re-entry:
1) Set status to 10b (debug-busy) .
2) Pop the return address from the stack .
3) Set the IGE bit to 1 if debug mode was activated when IGE = 1 .
4) Supply the CPU with an instruction addressed by the return address .
5) Stall the CPU at the end of the instruction execution .
6) Block the next instruction fetch from program memory .
7) Push the return address onto the stack .
8) Save and clear the UPA bit .
9) Set the contents of IP to 8010h .
10) Clear the IGE bit to 0 to disable the interrupt handler .
11) Halt CPU operation .
12) Set the status to debug-idle .
Note that the trace operation uses a return address from the stack as a legitimate address for program fetching . The
host must maintain consistency of program flow during the debug process . The instruction pointer is automatically
incremented after each trace operation, thus a new return address is pushed onto the stack before returning the con-
trol to the debug engine . Also, note that the interrupt handler is an essential part of the CPU and a pending interrupt
could be granted during single-step operation since the IGE bit state present on debug mode entry is restored for the
single step .
However, single tracing through program in system memory is prohibited by hardware if multiple memory regions are
defined .
12.3.4 Return
To terminate the debug mode and return the debug engine to background mode, the host must issue a return com-
mand to the debug engine . This command causes the following actions:
1) Pop the return address from the stack .
2) Restore the state of the UPA bit .
3) Set the IGE bit to 1 if debug mode was activated when IGE = 1 .
4) Supply the CPU with an instruction addressed by the return address .
5) Allow the CPU to execute the normal user program .
6) Set the status to 00b (nondebug) .
To prevent a possible endless breakpoint matching loop, no break occurs for a breakpoint match on the first instruc-
tion after returning from debug mode to background mode . Returning to background mode also enables all internal
timer functions .
12.3.5 Debug Mode Special Considerations
• The debug engine does not operate reliably when the CPU is in power-management mode (divide-by-256 system
clock mode) . To allow for proper execution of debug mode commands when invoked during PMM, the switchback
enable (SWB) bit should be configured to 1 . With SWB = 1, entering active debug mode (whether by breakpoint
match or issuance of the debug command) forces a switchback to the divide-by-1 system clock mode and allows
the debug engine to function correctly . This allows user code to configure breakpoints that occur inside PMM, thus
providing reliable use of debug commands . However, it does not allow a good means for re-entering PMM .