Maxim Integrated MAXQ610 - Manual (Page 64)

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MAXQ610 User’s Guide
REGISTER DESCRIPTION
SC, 08h[08h] System Control Register (16 bits)
Initialization This register is reset to 000001ss100000s0b on all resets . Bits 1, 8, and 9 (PWL, PWLS,
PWLL) are set to 1 on power-fail and power-on reset only .
Access Bits 8, 9, and 10 have write restrictions (see bit descriptions) . All other bits: unrestricted
read/write access .
SC.0 Reserved . All reads return 0 .
SC.1 (PWL) Password Lock Application. This bit defaults to 1 on power-fail and power-on reset .
When this bit is 1, it requires a 32-byte password to be matched with the password in the
user application program space before allowing access to the user-application password
protected in-circuit debug or bootstrap loader utility ROM routines . Clearing this bit to
0 disables the password protection for these utility ROM routines . ROM-assisted active
debug commands are always disallowed if the value at flash word address 000Eh is pro-
grammed (i .e .,
≠FFFFh) .
SC.2 (ROD) Utility ROM Operation Done . This bit is used to signify completion of a utility ROM opera-
tion sequence to the control units . This allows the debug engine to determine the status
of a utility ROM sequence . Setting this bit to 1 causes an internal system reset if the JTAG
SPE bit is also set . Setting the ROD bit clears the JTAG SPE bit if it is set, and the ROD bit
is automatically cleared by hardware once the control unit acknowledges the done indica-
tion .
SC.3 (UPA) Upper Program Access . The physical program memory is logically divided into four
pages; P0 and P1 occupy the lower 32KWords while P2 and P3 occupy the upper
32KWords . P0 and P1 are assigned to the lower half of the program space and are always
active . However, P2 and P3 must be implicitly activated in the upper half of the program
space by setting the UPA bit to 1 for normal program execution . When UPA bit is cleared
to 0, the upper program memory space is occupied by the utility ROM and the physical
data to be accessible as program memory . This bit is reserved and reads return 0 on all
parts with 64KB program memory or less .
SC.5 to SC.4
(CDA1, CDA0) Code Data Access Bits 1:0. The CDA bits are used to logically map physical program
memory page to the data space for read/write access:
CDA[1:0]
BYTE MODE
ACTIVE PAGE
WORD MODE
ACTIVE PAGE
00 P0 P0 and P1
01 P1 P0 and P1
10 P2 P2 and P3
11 P3 P2 and P3
The logical addresses are depending on which memory segment is executing .
CDA1 is reserved and reads return 0 on all parts with 64KB program memory or less .
CDA0 is reserved and reads return 0 on all parts with 32KB program memory or less .
SC.6 Reserved . All reads return 0 .
SC.7 (TAP) Test Access (JTAG) Port Enable . This bit controls whether the test access port special
function pins are enabled . The TAP defaults to being enabled . Clearing this bit to 0 dis-
ables the TAP special function pins .
SC.8 (PWLS) Password Lock System. This bit defaults to 1 on power-fail and power-on reset . When
this bit is 1, it requires a 32-byte password to be matched with the password in the system
program space before allowing access to the system password-protected in-circuit debug
or bootstrap loader utility ROM routines . Clearing this bit to 0 disables the password pro-
tection for these utility ROM routines . This register bit can only be written by utility ROM
code when PRIV = HIGH . ROM assisted active debug commands are always disallowed if
the value at flash word address 000Eh is programmed (i .e .,
≠FFFFh) .