Maxim Integrated MAXQ610 - Manual (Page 31)

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MAXQ610 User’s Guide
• Serial Port 0: assigned priority level 2
• Timer B0: assigned priority level 2
Because simultaneous interrupts are first evaluated according to assigned priority level, the IR timer interrupt is ser-
viced first . Once the IR timer interrupt source has been cleared, the serial port 0 and timer B0 interrupt sources are
evaluated . Both of these interrupt sources have been assigned to the same priority level (level 2), so the natural prior-
ity of each source is used to determine which is serviced first . The serial port 0 interrupt is serviced first as its natural
priority is 4, whereas timer B0 has natural priority 6 . If two interrupts that are grouped under the same natural priority
occur simultaneously, the order in which handling of the interrupts occurs is left to the discretion of user code (i .e ., user
code must decide what order to check the associated interrupt flags) .
For an unhandled interrupt, the interrupt handler vectors to flash address 0x98 if the user disables any of the inter-
rupts when an interrupt is triggered or when a medium priority interrupt occurs while in stop mode . A simple “RETI” is
required to be placed at 0x98 .
2.9.5 Interrupt Exception Window
An interrupt exception window is a noninterruptible execution cycle . During this cycle, the interrupt handler does not
respond to any interrupt requests . All interrupts that would normally be serviced during an interrupt exception window
are delayed until the next execution cycle .
Interrupt exception windows are used when two or more instructions must be executed consecutively without any
delays in between . There are two conditions in the MAXQ610 microcontroller that cause an interrupt exception window:
• Activation of the prefix register (PFX)
• Code memory access using the code pointer (CP)
When the prefix register (PFX) is activated by writing a value to it, it retains that value only for the next clock cycle . For
the prefix value to be used properly by the next instruction, the instruction that sets the prefix value and the instruction
that uses it must always be executed back to back . Therefore, writing to the PFX register causes an interrupt exception
window on the next cycle .
The one-cycle stall when using the code pointer is due to the fact that the current instruction could also be accessing
the stack .
If an interrupt occurs during an interrupt exception window, an additional latency of one cycle in the interrupt handling
is caused as the interrupt is not serviced until the next cycle .
2.10 Operating Modes
In addition to the standard program execution mode, the MAXQ610 can also be in three other operating modes . During
reset mode, the processor is temporarily halted by an external or internal reset source . During power-management
mode, the processor executes instructions at a reduced clock rate in order to decrease power consumption . Finally,
stop mode halts execution and all internal clocks (with the exception of the wake-up timer if enabled) to save power
until an external stimulus indicates that processing should be resumed .
2.11 Reset Mode
When the MAXQ610 microcontroller is in reset mode, no instruction execution or other system or peripheral operations
occur, and all input/output pins return to default states . Once the condition that caused the reset (whether internal or
external) is removed, the processor begins executing code from utility ROM at address 8000h .
There are four different sources that can cause the MAXQ610 to enter reset mode:
• Power-on/power-fail reset
• External reset
• Watchdog timer reset
• Internal system reset