Maxim Integrated MAXQ610 - Manual (Page 158)

12-7
MAXQ610 User’s Guide
12.3 Debug Mode
There are two ways to enter the debug mode from background mode:
• Issuance of the debug command directly by the host through the TAP communication port
or
• Breakpoint matching mechanism
The host can issue the debug background command to the debug engine . This direct debug mode entry is indeter-
ministic . The response time varies dependent on system conditions when the command is issued . The breakpoint
mechanism provides a more controllable response, but requires that the breakpoints be initially configured in back-
ground mode . No matter the method of entry, the debug engine takes control of the CPU in the same manner . Debug
mode entry is similar to the state machine flow of an interrupt except that the target execution address is 8010h in
utility ROM instead of the address specified by the IV register that is used for interrupts . On debug mode entry, the
following actions occur:
1) Block the next instruction fetch from program memory .
2) Push the return address onto the stack .
3) Save the state of the UPA bit and clear it .
4) Set the contents of IP to 8010h .
5) Clear the IGE bit to 0 to disable interrupt handler if it is not already clear .
6) Halt CPU operation .
Once in debug mode, further breakpoint matches or host issuance of the debug command are treated as no operations
and do not disturb debug engine operation . Entering debug mode also stops the clocks to all timers, including the
watchdog timer . Temporarily disabling these functions allows debug mode operations without disrupting the relation-
ship between the original user program code and hardware timed functions . No interrupt request can be granted since
the interrupt handler is also halted as a result of IGE = 0 .
12.3.1 Debug Mode Commands
The debug engine sets the data shift register status bits to 01b (debug-idle) to indicate that it is ready to accept debug
commands from the host .
The host can perform the following operations from debug mode:
• Read register map
• Read program stack
• Read/write register
• Read/write data memory
• Single step of CPU (trace)
• Return to background mode
• Unlock password
The only operations directly controlled by the debug engine are single step and return . All other operations are assisted
by debug service routines contained in the utility ROM . These operations require that multiple bytes be transmitted
and/or received by the host, however each operation always begins with host transmission of a command byte . This
command byte is decoded by the debug engine in order to determine the quantity, sequence, and destination for
follow-on bytes received from the host . Even though there is no timing window specified for receiving the complete
command and follow-on data, the debug engine must receive the correct number of bytes for a particular command
before executing that command . If command and follow-on data are transmitted out of byte order or proper sequence,
the only way to resolve this situation is to disable the debug engine by changing the instruction regsiter (IR[2:0]) and