Maxim Integrated MAXQ610 - Manual (Page 129)

9-4
MAXQ610 User’s Guide
9.1.2 USART Mode 1
This mode provides asynchronous, full-duplex communication . A total of 10 bits is transmitted, consisting of a start bit
(logic 0), 8 data bits, and 1 stop bit (logic 1) as illustrated in Figure 9-2 . The data is transferred LSB first . The baud
rate is programmable through the baud-clock generator . Following a write to SBUF, the USART begins transmission
five cycles after the first baud clock from the baud-clock generator . Transmission takes place on the TXD pin . It begins
with the start bit being placed on the pin . Data is then shifted out onto the pin, LSB first . The stop bit follows . The TI bit
is set by hardware after the stop bit is placed on the pin . All bits are shifted out at the rate determined by the baud-
clock generator .
Once the baud-clock generator is active, reception can begin at any time . The REN bit (SCON .4) must be set to 1 to
allow reception . The detection of a falling edge on the RXD pin is interpreted as the beginning of a start bit and begins
the reception process . Data is shifted in at the selected baud rate . At the middle of the stop bit time, certain conditions
must be met to load SBUF with the received data:
RI must be 0, and either
If SM2 = 0, the state of the stop bit does not matter .
or
If SM2 = 1, the state of the stop bit must be 1 .
If these conditions are true, then SBUF (address) is loaded with the received byte, the RB8 bit (SCON .2) is loaded with
the stop bit, and the RI bit (SCON .0) is set . If these conditions are false, then the received data is lost (SBUF and RB8
not loaded) and RI is not set . Regardless of the receive word status, after the middle of the stop bit time, the receiver
goes back to looking for a 1-to-0 transition on the RXD pin .
Each data bit received is sampled on the 7th, 8th, and 9th clock used by the divide-by-16 counter . Using majority vot-
ing, two equal samples out of the three, determines the logic level for each received bit . If the start bit was determined
to be invalid (= 1), then the receiver goes back to looking for a 1-to-0 transition on the RXD pin in order to start the
reception of data .
9.1.3 USART Mode 2
This mode uses a total of 11 bits in asynchronous full-duplex communication as illustrated in Figure 9-3 . The 11 bits
consist of one start bit (a logic 0), 8 data bits, a programmable 9th bit, and one stop bit (a logic 1) . Like mode 1, the
transmissions occur on the TXD signal pin and receptions on RXD .
For transmission purposes, the 9th bit can be stuffed as a 0 or 1 . The 9th bit is transferred from the TB8 bit position in
the SCON register (SCON .3) following a write to SBUF to initiate a transmission . Transmission begins five clock cycles
after the first rollover of the divide-by-16 counter following a software write to SBUF . It begins with the start bit being
placed on the TXD pin . The data is then shifted out onto the pin, LSb first, followed by the 9th bit, and finally the stop
bit . The TI bit (SCON .1) is set when the stop bit is placed on the pin .
Once the baud-rate generator is active and the REN bit (SCON .4) has been set to 1, reception can begin at any time .
Reception begins when a falling edge is detected as part of the incoming start bit on the RXD pin . The RXD pin is then
sampled according to the baud rate speed . The 9th bit is placed in the RB8 bit location in SCON (SCON .2) . At the
middle of the 9th bit time, certain conditions must be met to load SBUF with the received data .
RI must be 0, and either
If SM2 = 0, the state of the 9th bit does not matter .
or
If SM2 = 1, the state of the 9th bit must be 1 .
If these conditions are true, then SBUF is loaded with the received byte, RB8 is loaded with the 9th bit, and RI is set .
If these conditions are false, then the received data is lost (SBUF and RB8 not loaded) and RI is not set . Regardless
of the receive word status, after the middle of the stop bit time, the receiver goes back to looking for a 1-to-0 transition
on RXD .