Table 3-3 . watchdog timeout period selection -20, Maxq610 user’s guide, Table 3-3. watchdog timeout period selection – Maxim Integrated MAXQ610 User Manual
Page 55
3-20
MAXQ610 User’s Guide
The watchdog timeout selection is made using bits WD1 (WDCN .5) and WD0 (WDCN .4) . The watchdog has four time-
out selections based on the system clock frequency as shown Figure 3-1 . Because the timeout is a function of the
system clock, the actual timeout interval is dependent on both the crystal frequency and the system clock mode selec-
tion . Table 3-3 shows a summary of the selectable watchdog timeout intervals for the various system clock modes and
WD[1:0] control bit settings . If enabled, the watchdog reset is always scheduled to occur 512 system clocks following
the timeout . Watchdog-generated resets last for eight system clock cycles .
Table 3-3. Watchdog Timeout Period Selection
SYSTEM CLOCK
MODE
SYSTEM CLOCK SELECT BITS
WATCHDOG TIMEOUT
(IN NUMBER OF OSCILLATOR CLOCKS)
PMME
CD1
CD0
WD[1:0] = 00b
WD[1:0] = 01b
WD[1:0] = 10b
WD[1:0] = 11b
Divide by 1 (default)
0
0
0
2
15
2
18
2
21
2
24
Divide by 2
0
0
1
2
16
2
19
2
22
2
25
Divide by 4
0
1
0
2
17
2
20
2
23
2
26
Divide by 8
0
1
1
2
18
2
21
2
24
2
27
Power-Management
Mode (Divide by 256)
1
x
x
2
23
2
26
2
29
2
32