Maxim Integrated MAXQ610 - Manual (Page 3)

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MAXQ610 User’s Guide
SECTION 1: OVERVIEW
The MAXQ M family of 16-bit reduced instruction set computing (RISC) microcontrollers is targeted towards low-cost,
low-power embedded application designs . The flexible, modular architecture design used in these microcontrollers
allows development of targeted designs for specific applications with minimal effort .
1.1 Instruction Set
The MAXQ610 microcontroller uses an instruction set where all instructions are fixed in length (16 bits) . A register-
based, transport-triggered architecture allows all instructions to be coded as simple transfer operations . All instruc-
tions reduce to either writing an immediate value to a destination register or memory location or moving data between
registers and/or memory locations .
This simple top-level instruction decoding allows all instructions to be executed in a single cycle . Because all CPU
operations are performed on registers only, any new functionality can be added by simply adding new register mod-
ules . The simple instruction set also provides maximum flexibility for code optimization by a compiler .
1.2 Harvard Memory Architecture
Program memory, data memory, and register space on the MAXQ610 are separate from one another and are each
accessed by a separate bus . This type of memory architecture (known as Harvard architecture) has some advantages .
First, the word lengths can be different for different types of memory . Program memory must be 16 bits wide to accom-
modate the instruction word size, but system and peripheral registers can be 8 bits wide or 16 bits wide as needed .
Because data memory is not required to store program code, its width can also vary and could conceivably be targeted
for a specific application .
Also, because data memory is accessed by the CPU only through appropriate registers, it is possible for register
modules to access memory entirely independent from the main processor, providing the framework for direct memory
access operations . It is also possible to have more than one type of data memory, each accessed through a different
register set .
1.3 Register Set
Because all functions in the MAXQ610 family are accessed through registers, common functionality is provided through
a common register set . Many of these registers provide the equivalent of higher level op codes, by directly accessing
the ALU, the loop counter registers, and the data pointer registers . Others, such as the interrupt registers, provide
common control and configuration functions that are equivalent across the MAXQ610
family of microcontrollers .
The common register set, also known as the system registers, includes the following:
• Arithmetic logic unit (ALU) access and control registers, including working accumulator registers and the processor
status flags
• Two data pointers and a frame pointer for data memory access
• Autodecrementing loop counters for fast, compact looping
• Instruction pointer and other branching control access points
• Stack pointer and an access point to the 16-bit-wide soft stack
• Interrupt vector table and priority registers
• One code pointer for quick program memory access as data
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