Maxim Integrated MAXQ610 - Manual (Page 178)

14-11
MAXQ610 User’s Guide
Table 14-3. Destination Specifier Codes
dst
dst BIT
ENCODING
ddd dddd
WIDTH
16 OR 8
DESCRIPTION
NUL 111 0110 8/16
Null (Virtual) Destination; Intended As A Bit Bucket to Assist Software with
Pointer Increments/Decrements
MN[n] nnn 0NNN 8/16
nnnn Selects One of 1st Eight Registers in Module NNN, where NNN = 0
to 5; Access to Next 24 Using PFX[n]
AP 000 1000 8 Accumulator Pointer
APC 001 1000 8 Accumulator Pointer Control
PSF 100 1000 8 Processor Status Flag Register
IC 101 1000 8 Interrupt and Control Register
A[n] nnn 1001 8/16 nnn Selects One of 1st Eight Accumulators: A[0] to A[7]
Acc 000 1010 8/16 Active Accumulator = A[AP]
PFX[n] nnn 1011 8 nnn Selects One of Eight Prefix Registers
@++SP 000 1101 16 16-Bit Word @SP, Push (predecrement SP)
SP 001 1101 16 Stack Pointer
IV 010 1101 16 Interrupt Vector
LC[n] 11n 1101 16 n Selects One of Two Loop Counter Registers
@BP[OFFS] 000 1110 8/16 Data Memory @BP[OFFS]
@BP[++OFFS] 001 1110 8/16 Data Memory @BP[OFFS]; Preincrement OFFS
@BP[--OFFS] 010 1110 8/16 Data Memory @BP[OFFS]; Predecrement OFFS
OFFS 011 1110 8 Frame Pointer Offset from Base Pointer (BP)
DPC 100 1110 16 Data Pointer Control Register
GR 101 1110 16 General Register
GRL 110 1110 8 Low Byte of GR Register
BP 111 1110 16 Frame Pointer Base Pointer (BP)
@DP[n] n00 1111 8/16 Data Memory @DP[n]
@++DP[n] n01 1111 8/16 Data Memory @DP[n], Preincrement DP[n]
@--DP[n] n10 1111 8/16 Data Memory @DP[n], Predecrement DP[n]
DP[n] n11 1111 16 n Selects One of Two Data Pointers
2-CYCLE DESTINATION ACCESS USING PFX[n] Register (see Special Notes)
SC
000 1000 16 System Control Register
IPR0 001 1000 16 Interrupt Priority Register Zero
CKCN 110 1000 8 Clock Control Register
WDCN 111 1000 8 Watchdog Control Register
A[n] nnn 1001 16 nnn Selects One of 2nd Eight Accumulators A[8] to A[15]
GRH 001 1110 8 High Byte of GR Register
CP 011 1111 16 Code Pointer