Maxim Integrated MAXQ610 - Manual (Page 141)

10-5
MAXQ610 User’s Guide
The application software must correct the system conflict before resuming its normal operation . The MODF flag is set
automatically by hardware, but must be cleared by software or a reset once set . Setting the MODF bit to 1 by software
causes an interrupt if enabled .
Mode fault detection is optional and can be disabled by clearing the MODFE bit to 0 . Disabling the mode fault detection
disables the function of the SSEL signal during master mode operation, allowing the associated port pin to be used as
a general-purpose I/O .
Note that the mode fault mechanism does not provide full protection from bus contention in multiple master, multiple
slave systems . For example, if two devices are configured as master at the same time, the mode fault-detect circuitry
offers protection only when one of them selects the other as slave by asserting its SSEL signal . Also, if a master acci-
dentally activates more than one slave and those devices try to simultaneously drive their output pins, bus contention
can occur without and a mode fault error being generated .
10.5.2 Receive Overrun
Since the receive direction of SPI is double buffered, there is no overrun condition as long as the received character in
the read buffer is read before the next character in the shift register ready to be transferred to the read buffer . However,
if previous data in the read buffer has not been read out when a transfer cycle is completed and the new character
is loaded into the read buffer, a receive overrun occurs and the receive overrun flag (SPICN .5: ROVR) is set . Setting
the ROVR flag indicates that the oldest received character has been overwritten and is lost . Setting the ROVR bit to 1
causes an interrupt if enabled . Once set, the ROVR bit is cleared only by software or a reset .
10.5.3 Write Collision While Busy
A write collision occurs if an attempt to write the SPIB data buffer is made during a transfer cycle (STBY = 1) . Since the
shift register is single buffered in the transmit direction, writes to SPIB are made directly into the shift register . Allowing
the write to SPIB while another transfer is in progress could easily corrupt the transmit/receive data . When such a write
attempt is made, the current transfer continues undisturbed, the attempted write data is not transferred to the shift reg-
ister, and the control unit sets the write collision flag (SPICN .4: WCOL) . Setting the WCOL bit to 1 causes an interrupt
if SPI interrupt sources are enabled . Once set, the WCOL bit is cleared only by software or a reset .
Normally, write collisions are associated solely with slave devices since they do not control initiation of transfers and
do not have access to as much information about the SPICK clock as the master . As a master, write collisions are
completely avoidable, however, the control unit detects write collisions for both master and slave modes .
10.6 SPI Master Operation
The SPI module is placed in master mode by setting the master mode enable bit (MSTM) in the SPI control register to
1 . Only an SPI master device can initiate a data transfer . The master is responsible for manually selecting/deselecting
slave(s) through the SSEL slave input signals . Writing a data character to the SPI shift register (SPIB) while in master
mode starts a data transfer . The SPI master immediately shifts out the data serially on the MOSI pin, most significant
bit first, while providing the serial clock on SPICK output . New data is simultaneously received on the MISO pin into the
least significant bit of the shift register . The data transfer format (clock polarity and phase), character length, and baud
rate are all configurable as described earlier in the section . During the transfer, the SPI transfer busy flag (SPICN .7:
STBY) is set to indicate that a transfer is in process . At the end of the transfer, the data contained in the shift register is
moved into the receive data buffer, the STBY bit is cleared by hardware, and the SPI transfer complete flag (SPICN .6:
SPIC) is set . Setting of the SPIC bit generates an interrupt request if SPI interrupt sources are enabled (ESPII = 1) .
10.7 SPI Slave Operation
The SPI module operates in slave mode when the MSTM bit is cleared to 0 . In slave mode, the SPI is dependent on
the SPICK sourced from the master to control the data transfer . The SPICK input frequency should be no greater than
the system clock of the slave device frequency divided by 4 .
The slave-select SSEL input must be externally asserted by a master before data exchange can take place . SSEL
must be asserted before data transaction begin and must remain asserted for the duration of the transaction . If data
is to be transmitted by the slave device, it must be written to its shift register before the beginning of a transfer cycle,
otherwise the character already in the shift register is transferred . The slave device considers a transfer to begin with