Maxim Integrated MAXQ610 - Manual (Page 166)

13-2
MAXQ610 User’s Guide
SECTION 13: IN-SYSTEM PROGRAMMING (JTAG)
Internal nonvolatile (flash) memory of MAXQ610 microcontrollers can be initialized through bootstrap-loader mode .
To enable the bootstrap loader and establish a desired communication channel, the system programming instruction
(100b) must be loaded into the TAP instruction register using the IR-scan sequence . Once the instruction is latched in
the instruction parallel buffer (IR[2:0]) and is recognized by the TAP controller in the update-IR state, a 3-bit data shift
register is activated as the communication channel for DR-scan sequences . The TAP retains the system programming
instruction until a new instruction is shifted in or the TAP controller returns to the test-logic-reset state . This 3-bit shift
register formed between the TDI and TDO pins is directly interfaced to the 3-bit serial programming buffer (SPB) . The
system programming buffer (SPB) contains three bits with the following functions:
• SPB.0—System Programming Enable (SPE). Setting this bit to a 1 denotes that system programming is desired upon
exiting reset . When it is cleared to 0, no system programming is needed . The logic state of SPE is examined by
the reset vector in the utility ROM to determine the program flow after a reset . When SPE = 1, the bootstrap loader
selected by the PSS[1:0] bits is activated to perform a bootstrap-loader function . When SPE = 0, the utility ROM
transfers execution control to the normal user program .
• SPB.2:1—Programming Source Select (PSS[1:0]). These bits allow the host to select programming interface sources.
The PSS bits have no functions when the SPE bit is cleared .
The DR-scan sequence is used to configure the SPB bits . The data content of the SPB register is reflected in the ICDF
register and allows read/write access by the CPU . These bits are cleared by power-on reset or test-logic-reset of the
TAP controller .
13.1 JTAG Bootloader Operation
Devices that support a JTAG bootloader have the benefit of using the same status bit handshaking hardware as is used
for in-circuit debugging . When the SPE bit of the system programming buffer (SPB) is set to 1 and JTAG is selected
as the programming source (PSS[1:0] = 00b), the background and active debug mode state machines are disabled .
Once the host loads the debug instruction into the TAP instruction register (IR[2:0]), the 10-bit shift register interface
to ICDB and the status bits become available for host-to-utility ROM bootloader communication . The status bits should
be interpreted as shown in Table 13-1 for JTAG bootloader operation:
When the using the JTAG bootloader option (SPE = 1, PSS[1:0] = 00b), the sole purpose of the debug hardware is
to simultaneously transfer the data byte shifted in from the host into the ICDB register and transfer the contents of an
internal holding register (loaded by utility ROM code writes of ICDB) into the shift register for output to the host . This
transfer takes place on the falling edge of TCK at the update-DR state . The debug hardware additionally clears the TXC
bit at this point in the state diagram . The utility ROM loader code controls the status bit output to the host by asserting
TXC = 1 when it has valid data to be shifted out . The utility ROM code can flexibly implement whatever communication
protocol and command set it wishes within the data byte portion of the shifted 10-bit word .
Table 13-1. Status Bits for Bootloader Operation
PSS1 PSS0 PROGRAMMING SOURCE
0 0 JTAG
0 1 Reserved
1 0 Reserved
1 1 Reserved
BITS 1:0 STATUS CONDITION
00 Reserved Invalid condition
01 Reserved Invalid condition
10 Loader-Busy Utility ROM loader is busy executing code or processing the current command
11 Loader-Valid Utility ROM loader is supplying valid output data to the host in current shift operation