Maxim Integrated MAXQ610 - Manual (Page 125)

8-12
MAXQ610 User’s Guide
Bit 1: IR Interrupt Flag (IRIF). This flag is set to 1 during transmit when the IR timer reloads its value and in receive
mode (if RXBCNT = 0), when a capture occurs . In receive mode (when RXBCNT = 1), this flag is set whenever the
IRCA x 2 interval timer expires . This bit must be cleared to 0 by software once it is set .
Bit 0: IR Timer Overflow Flag (IROV). This flag is set to 1 when the IR timer overflows from 0FFFFh to 0000h in receive
mode . This bit must be cleared to 0 by software once it is set .
8.7.3 IR Value Register (IRV)
The IRV register is a 16-bit register that holds the current IR timer value . The IR timer value starts counting when the
IREN bit is set to 1 . It stops counting when the IREN bit is cleared to 0 and retains the current timer value .
8.7.4 IR Carrier Register (IRCA)
Bits 15 to 8: IR Carrier High Byte Bits [7:0] (IRCAH[7:0]). The IRCAH byte defines the number of IR input clocks
during carrier high time . The carrier high time = IRCAH[7:0] + 1 .
Bits 7 to 0: IR Carrier Low Byte Bits [7:0] (IRCAL[7:0]). The IRCAL byte defines the number of IR input clocks during
carrier low time . The carrier low time = IRCAL[7:0] + 1 .
8.7.5 IR Modulator Time Register (IRMT)
The IRMT register is a 16-bit register that defines the IRDATA active time during transmit mode . In receive mode (when
RXBCNT = 0), it is used to capture the IRV value on qualified IRRXSEL edges . In receive mode (when RXBCNT = 1),
the IRMT register increments on detection of selected IRRXSEL edge(s) . When RXBCNT is changed from 0 to 1, the
IRMT register is set to 0001h by hardware .
15 0
IR Value Register (IRV)
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Power-On Reset and System Resets
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IR Carrier Register (IRCA)
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Power-On Reset and System Resets
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IR Modulator Time Register (IRMT)
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Power-On Reset and System Resets
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