Maxim Integrated MAXQ610 - Manual (Page 78)

5-6
MAXQ610 User’s Guide
REGISTER DESCRIPTION
EIF1 (06h, 00h) External Interrupt Flag 1 Register
Initialization: EIF1 is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write .
EIF1.7 to EIF1.0 (IE[15:8]) Interrupt Edge Detect Bits 15:8. These bits are set when a negative edge (ITn = 1) or a
positive edge (ITn = 0) is detected on the interrupt n pin . Setting any of the bits to 1 gener-
ates an interrupt to the CPU if the corresponding interrupt is enabled . The bit remains set
until cleared by software or a reset . It must be cleared by software before exiting the inter-
rupt source routine or another interrupt is generated as long as the bit remains set .
Note: For the 32-pin package, the INT8 to INT15 functions are not present on external pins,
however, the associated interrupt registers (EIE1, EIF1, EIES1) are still present . Software
should not write to the EIF1 register as this could trigger an unplanned interrupt condition if
EIE1 and EIES1 are used for general purpose .
EIE1 (07h, 00h) External Interrupt Enable 1 Register
Initialization: EIE1 is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write .
EIE1.7 to EIE1.0 (EX[15:8]) Enable External Interrupt Bits 15:8. Setting any of these bits to 1 enables the correspond-
ing external interrupt . Clearing any of the bits to 0 disables the corresponding interrupt
function .
Note: For the 32-pin package, the INT8 to INT15 functions are not present on external pins .
This register can be used as a general-purpose register as long as the user software does
not write to the EIF1 flag register since this could trigger an unplanned interrupt condition .
PI0 (08h, 00h) Port 0 Input Register
Initialization: The reset value for this register is dependent on the logical states of the pins .
Read/Write Access: Unrestricted read-only .
PI0.7 to PI0.0 Port 0 Input Register Bits 7:0. The PI0 register always reflects the logic state of its pins
when read . Note that each port pin has a weak pullup circuit when functioning as an input
and the p-channel pullup transistor is controlled by its respective PO bits . If the PO bit is set
to 1, the weak pullup is on, if the PO bit is cleared to 0, the weak pullup is off and forces the
port pin into three-state .
PI1 (09h, 00h) Port 1 Input Register
Initialization: The reset value for this register is dependent on the logical states of the pins .
Read/Write Access: Unrestricted read .
PI1.7 to PI1.0 Port 1 Input Register Bits 7:0. The PI1 register always reflects the logic state of its pins
when read . Note that each port pin has a weak pullup circuit when functioning as an input
and the p-channel pullup transistor is controlled by its respective PO bits . If the PO bit is set
to 1, the weak pullup is on, if the PO bit is cleared to 0, the weak pullup is off and forces the
port pin into three-state .
PI2 (0Ah, 00h) Port 2 Input Register
Initialization: The reset value for this register is dependent on the logical states of the pins .
Read/Write Access: Unrestricted read .
PI2.7 to PI2.0 Port 2 Input Register Bits 7:0. The PI2 register always reflects the logic state of its pins
when read . Note that each port pin has a weak pullup circuit when functioning as an input
and the p-channel pullup transistor is controlled by its respective PO bits . If the PO bit is set
to 1, the weak pullup is on, if the PO bit is cleared to 0, the weak pullup is off and forces the
port pin into three-state .