Maxim Integrated MAXQ610 - Manual (Page 142)

10-6
MAXQ610 User’s Guide
the first clock edge or the active SSEL edge, dependent on the data transfer format . When SAS is cleared to 0, the
active SSEL edge is the falling edge of SSEL, while if SAS is set to 1, the active SSEL edge is the rising edge of SSEL .
The SPI slave receives data from the external master MOSI pin, most significant bit first, while simultaneously transfer-
ring the contents of its shift register to the master on the MISO pin, also most significant bit first . Data received from the
external master replaces data in the internal shift register until the transfer completes . Just like in the master mode of
operation, received data is loaded into the read buffer and the SPI transfer complete flag is set at the end of transfer .
The setting of the transfer complete flag generates an interrupt request if enabled . Note also that when CKPHA = 0,
the most significant bit of the SPI data buffer is shifted out on the 8th shift clock edge .
When SSEL is not asserted, the slave device ignores the SPICK clock and the shift register is disabled . Under this
condition, the device is basically idle, no data is shifted out from the shift register and no data is sampled from the
MOSI pin . The MISO pin is placed in an input mode and is weakly pulled high to allow other devices on the bus to drive
the bus . Deassertion of the SSEL signal by the master during a transfer (before a full character, as defined by CHR, is
received) aborts the current transfer . When the transfer is aborted, no data is loaded into the read buffer, the SPIC flag
is not set, and the slave logic and the bit counter are reset .
In slave mode, the clock divider ratio bits (CKR[7:0]) have no function since the serial clock is supplied by an external
master . The transfer format (CKPOL, CKPHA settings) and the character length selection (CHR) for the slave device,
however, should match the master for a proper communication .
10.8 SPI Peripheral Registers
10.8.1 SPI Control Register (SPICN)
Bit 7: SPI Transfer Busy Flag (STBY). This bit is used to indicate the current transmit/receive activity of the SPI mod-
ule . STBY is set to 1 when an SPI transfer cycle starts, and is cleared to 0 when the transfer cycle is completed . This
bit is controlled by hardware and is read only for user software .
0 = SPI module is idle—no transfer in process
1 = SPI transfer in process
Bit 6: SPI Transfer Complete Flag (SPIC). This bit signals the completion of an SPI transfer cycle . This bit must be
cleared to 0 by software once set . Setting this bit to 1 causes an interrupt if enabled .
0 = No SPI transfers have completed since the bit was last cleared .
1 = SPI transfer complete
Bit 5: Receive Overrun Flag (ROVR). This bit indicates when a receive overrun has occurred . A receive overrun
results when a received character is ready to be transferred to the SPI receive data buffer before the previous charac-
ter in the data buffer is read . The most recent receive data is lost . This bit must be cleared to 0 by software once set .
Setting this bit to 1 causes an interrupt if enabled .
0 = No receive overrun has occurred
1 = Receive overrun occurred
Bit 4: Write Collision Flag (WCOL). This bit signifies that an attempt was made by software to write the SPI buffer
(SPIB) while a transfer was in progress (STBY = 1) . Such attempts are always blocked . This bit must be cleared to 0
by software once set . Setting this bit to 1 causes an interrupt if enabled .
0 = No write collision has been detected
1 = Write collision detected
7 0
SPI Control Register (SPICN)
0 0 0 0 0 0 0 0 Power-On Reset and System Resets
r rw rw rw rw rw rw rw Read (r), Write (w), or Special (s) access