Maxim Integrated MAXQ610 - Manual (Page 140)

10-4
MAXQ610 User’s Guide
10.2 SPI Slave Select
The SPI slave-select SSEL can be configured to accept either an active-low or active-high SSEL signal through the
slave active select bit (SAS) in the SPI configuration register . The SAS bit allows the selection of the SSEL asserted
state .
When SAS is cleared to 0, SSEL is configured to be asserted low . When SAS is set to 1, SSEL is configured to be
asserted high .
10.3 SPI Character Lengths
To flexibly accommodate different SPI transfer data lengths, the character length for any transfer is user configurable
through the character length bit (CHR) in the SPI configuration register . The CHR bit allows selection of either 8-bit or
16-bit transfers .
When loading 8-bit characters into the SPIB data buffer, the byte for transmission should be right-justified or placed
in the least significant byte of the word . When a byte transfer completes, the received byte is right-justified and can
be read from the least significant byte of the SPIB word . The most significant byte of the SPIB data buffer is not used
when transmitting and receiving 8-bit characters .
10.4 SPI Transfer Baud Rates
When operating as a slave device, the SPI serial clock is driven by an external master . For proper slave operation, the
serial clock provided by the external master should not exceed the system clock frequency divided by 4 .
When operating in the master mode, the SPI serial clock is sourced to the external slave device(s) . The serial clock
baud rate is determined by the clock divide ratio specified in the SPI clock divider ratio (SPICK) register . The SPI mod-
ule supports 256 different clock divide ratio selections for serial clock generation . The SPICK clock rate is determined
by the following formula:
SPI Baud Rate = System Clock Frequency/2 x Clock Divider Ratio
where clock divider ratio = (SPICK[7:0]) + 1
Since the SPI baud rate is a function of the system clock frequency, using any of the system clock divide modes
(including power-management mode) alters the baud rate . Attempts to invoke the power-management mode while an
SPI transfer in is progress (STBY = 1) are ignored .
Note, however, that once in power-management mode (PMME = 1), writes to SPIB in master mode and assertion of the
SSEL pin in slave mode both qualify as switchback sources if enabled (SWB = 1) . The SPI module clocks are halted if
the device is placed into stop mode .
10.5 SPI System Errors
Three types of SPI system errors can be detected by the SPI module . A mode fault error arises in a multiple master
system when more than one SPI device simultaneously tries to be a master . A receive overrun error occurs when an SPI
transfer completes before the previous character has been read from the receive holding buffer . The third kind of error,
write collision, indicates that an attempted write to SPIB was detected while a transfer was in progress (STBY = 1) .
10.5.1 Mode Fault
When an SPI device is configured as a master and its mode fault enable bit (SPICN .2: MODFE) is also set, a mode fault
error occurs if the SSEL input signal is asserted by an external device . The asserted state of SSEL is defined by slave
active select bit (SPICN .6: SAS) . If SAS is cleared to 0 and a low SSEL input signal is detected while MODFE is set,
a mode fault error has occurred . If SAS is set to 1, a high SSEL signal indicates that a mode fault error has occurred .
The mode fault error detection is to provide protection from such damage by disabling the bus drivers . When a mode
fault is detected, the following actions are taken immediately:
1) The MSTM bit is forced to 0 to reconfigure the SPI device as a slave .
2) The SPIEN bit is forced to 0 to disable the SPI module .
3) The mode fault status flag (SPICN .3: MODF) is set . Setting the MODF bit can generate an interrupt if it is enabled .