Maxim Integrated MAXQ610 - Manual (Page 35)

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MAXQ610 User’s Guide
Note that the voltage monitor and bandgap reference can be disabled during stop mode to conserve current consump-
tion . In this case, a power-fail condition does not cause a reset as it would under normal conditions . However, the POR
monitor remains enabled, and any voltage drop on V
DD that goes below the POR level causes a POR to occur . To
continue to monitor supply voltage during stop mode, the power-fail monitor is left on if the regulator is left on (REGEN
= 1), or it can be explicitly enabled (if the regulator is disabled; REGEN = 0) by clearing the PWCN .PFD bit to 0 . The
power-fail monitor is always enabled prior to stop mode exit and resumption of code execution .
Once the processor exits stop mode, it resumes execution as follows:
• If the crystal oscillator is selected as the system clock source, the crystal oscillator is started and execution resumes
following an 8192-clock-cycle delay to allow the oscillator frequency to stabilize .