Maxim Integrated MAXQ610 - Manual (Page 9)

2-5
MAXQ610 User’s Guide
The MAXQ instruction set is designed to be highly orthogonal . All arithmetic and logical operations that use two reg-
isters can use any register along with the accumulator . Data can be transferred between any two registers in a single
instruction .
2.2 Register Space
The MAXQ610 provides a total of 16 register modules . Each of these modules contains 32 registers . The first eight
registers in each module can be read from or written to in a single cycle; the second eight registers can be read from
in a single cycle and written to in two cycles (by using the prefix register, PFX); the last 16 registers can be read or
written in two cycles (always requiring use of the prefix register, PFX) .
Registers can be either 8 or 16 bits in length . Within a register, any number of bits can be implemented; bits not
implemented are fixed at zero . Data transfers between registers of different sizes are handled as shown in Table 2-1 .
• If the source and destination registers are both 8 bits wide, data is transferred bit to bit accordingly.
• If the source register is 8 bits wide and the destination register is 16 bits wide, the data from the source register is
transferred into the lower 8 bits of the destination register . The upper 8 bits of the destination register are set to the
current value of the prefix register; this value is normally zero, but it can be set to a different value by the previous
instruction if needed . The prefix register reverts back to zero after one cycle, so this must be done by the instruction
immediately before the one that would be using the value .
• If the source register is 16 bits wide and the destination register is 8 bits wide, the lower 8 bits of the source are
transferred to the destination register .
• If both registers are 16 bits wide, data is copied bit to bit.
The above rules apply to all data movements between defined registers . Data transfer to/from undefined register loca-
tions has the following behavior:
• If the destination is an undefined register, the MOVE is a dummy operation, but can trigger an underlying operation
according to the source register (e .g ., @DP[n]--) .
• If the destination is a defined register and the source is undefined, the source data for the transfer depends upon the
source module width . If the source is from a module containing 8-bit or 8-bit and 16-bit source registers, the source
data is equal to the prefix data concatenated with 00h . If the source is from a module containing only 16-bit source
registers, 0000h source data is used for the transfer .
The 16 available register modules are broken up into two different groups . The low six modules (specifiers 0h to5h) are
known as the peripheral register modules, while the high 10 modules (specifiers 6h to 0Fh) are known as the system
register modules . These groupings are descriptive only, as there is no difference between accessing the two register
groups from a programming perspective .
The system registers define basic functionality that remains the same across all products based on the MAXQ610
architecture . This includes all register locations that are used to implement higher level op codes as well as the follow-
ing common system features:
• ALU (16 bits) and associated status flags (zero, equals, carry, sign, overflow)
• 16 working accumulator registers (16-bit width), along with associated control registers
• Instruction pointer
• Registers for interrupt control and handling
• Autodecrementing loop counters for fast, compact looping
• Two data pointer registers, a frame pointer, and a stack pointer for data memory/stack access
• One code pointer register for program memory access
The peripheral registers define additional functionality included in the MAXQ610 . This functionality is broken up into
discrete modules so that only the features that are required for a given product need to be included . Because the
peripheral registers add functionality outside the common MAXQ system architecture, they are not used to implement
op codes .