Maxim Integrated MAXQ610 - Manual (Page 29)

2-25
MAXQ610 User’s Guide
is set, even if the interrupt source is disabled at the local or global level . Interrupt flags must be cleared within the user
interrupt routine to avoid repeated interrupts from the same source .
The handler uses three levels of interrupt priorities that allow the user software to select a suitable priority for an inter-
rupt vector source . The interrupt handler (hardware) modifies the interrupt priority status bits (IPSn) when it is servicing
an interrupt . These bits are set to 11b by the interrupt handler when executing a RETI instruction .
2.9.2 Interrupt System Operation
The interrupt handler responds to any interrupt event when it is enabled . An interrupt event occurs when an interrupt
flag is set . All interrupt requests are sampled at the rising edge of the clock, and can be served by the processor one
clock cycle later, assuming the request does not hit the interrupt exception window . The one cycle stall between detec-
tion and acknowledgement/servicing is due to the fact that the current instruction could also be accessing the stack,
or that the current instruction could be a prefix (PFX) write . For this reason, the CPU must allow the current instruction
to complete before pushing the stack and vectoring to the proper interrupt vector table address . If an interrupt excep-
tion window is generated by the currently executing instruction, the following instruction must be executed, thus the
interrupt service routine is delayed an additional cycle .
Interrupt operation in the MAXQ610 CPU is essentially a state-machine-generated long CALL instruction . When the
interrupt handler services an interrupt, it temporarily takes control of the CPU to perform the following sequence of
actions:
1) The next instruction fetch from program memory is cancelled .
2) The return address is pushed on to the stack .
3) The IPS bits are set to the current interrupt level to prevent recursive interrupt calls from interrupts of lower priority .
4) The instruction pointer is set to the location of the interrupt service routine as defined by the interrupt source .
5) The CPU begins executing the interrupt service routine .
Once the interrupt service routine completes, it should use the RETI instruction to return to the main program . Execution
of RETI involves the following sequence of actions:
1) The return address is popped off the stack .
2) The IPS bits are set to 11b to re-enable interrupt handling .
3) The instruction pointer is set to the return address that was popped off the stack .
4) The CPU continues execution of the main program .
Pending interrupt requests do not interrupt a RETI instruction; a new interrupt is serviced after first being acknowledged
in the execution cycle that follows the RETI instruction and then after the standard one stall cycle of interrupt latency .
This means there are at least two cycles between back-to-back interrupts .
2.9.3 Synchronous vs. Asynchronous Interrupt Sources
Interrupt sources can be classified as either asynchronous or synchronous . All internal interrupts are synchronous inter-
rupts . An internal interrupt is directly routed to the interrupt handler that can be recognized in one cycle . All external
interrupts are asynchronous interrupts by nature . Asynchronous interrupt sources are passed through a three-clock
sampling/glitch filter circuit before being routed to the interrupt handler . The sampling/glitch filter circuit is running on
the undivided source clock (i .e ., before PMME, CD[1:0] controlled clock divide) such that the number of system clocks
required to recognize an asynchronous interrupt request depend upon the system clock divide ratio:
• If the system clock-divide ratio is 1, the interrupt request is recognized after three system clocks.
• If the system clock-divide ratio is 2, the interrupt request is recognized after two system clocks.
• If the system clock divide ratio is 4 or greater, the interrupt request is recognized after one system clock.
An interrupt request with pulse width less than three undivided clock cycles is not recognized .
Note that the granularity of interrupt source is at module level . Synchronous interrupts and sampled asynchronous
interrupts assigned to the same module product a single interrupt to the interrupt handler .