Maxim Integrated MAXQ610 - Manual (Page 33)

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MAXQ610 User’s Guide
POR level, a POR is generated . The power-fail monitor is enabled prior to the stop mode exit and before code execu-
tion begins . If a power-fail warning condition (V
DD < V PFW ) is then detected, the power-fail interrupt flag is set on stop
mode exit . If a power-fail reset condition is detected (V DD < V RST ), the CPU goes into reset .
2.11.2 External Reset
During normal operation, the MAXQ610 device is placed into external reset mode by holding the RESET pin low for
at least four clock cycles . If the MAXQ610 is in the low-power stop mode (i .e ., system clock is not active), the RESET
pin becomes an asynchronous source, forcing the reset state immediately after being taken low . Once the MAXQ610
enters reset mode, it remains in reset as long as the RESET pin is held low . After the RESET pin returns to high, the pro-
cessor exits the reset state within four clock cycles and begins program execution from utility ROM at address 8000h .
The RESET pin is an output as well as an input . If a reset condition is caused by another source (such as a power-fail
reset or internal reset), an output reset pulse is generated at the RESET pin for as long as the MAXQ610 remains in
reset . If the RESET pin is connected to an RC reset circuit or a similar circuit, it may not be able to drive the output
reset signal; however, if this occurs, it does not affect the internal reset condition .
2.11.3 Watchdog Timer Reset
The watchdog timer is a programmable hardware timer that can be set to reset the processor in the case of a soft-
ware lockup or other unrecoverable error . Once the watchdog is enabled in this manner, the processor must reset the
watchdog timer periodically to avoid a reset . If the processor does not reset the watchdog timer before it elapses, the
watchdog initiates a reset state .
If the watchdog resets the processor, it remains in reset for four clock cycles . Once the reset condition is removed, the
processor begins executing program code from utility ROM at address 8000h . When a reset occurs due to a watch-
dog timeout, the watchdog timer reset flag in the WDCN register is set to 1 and can only be cleared by software . User
software can examine this bit following a reset to determine if that reset was caused by a watchdog timeout .
2.11.4 Internal System Reset
The MAXQ610 can incorporate functions that logically warrant the ability to generate an internal system reset . This
reset generation capability is assessed by MAXQ610 function based upon its expected use . In-system programming
is a prime example of functionality that benefits by having the ability to reset the device . The exact in-system program-
ming protocol is somewhat device- and interface-specific, however, it is expected that, upon completion of in-system
programming, many users will want the ability to reset the system . This internal (software-triggered) reset generation
capability is possible following in-system programming .
2.12 Power-Management Mode
There are two major sources of power dissipation in CMOS circuitry . The first is static dissipation caused by continu-
ous leakage current . The second is dynamic dissipation caused by transient switching current required to charge and
discharge load capacitors as well as short-circuit current produced by momentary connections between V
DD and
ground during gate switching .
Usually it is the dynamic switching power dissipation that dominates the total power consumption, and this power dis-
sipation (P
D ) for a CMOS circuit can be calculated in terms of load capacitance (C L ), power-supply voltage (V DD ),
and operating frequency (f) as:
P
D
= C
L
O V
DD2
O f
Capacitance and supply voltage are technology dependent and relatively fixed . However, the operating frequency
determines the clock rate, and the required clock rate can be different from application to application depending on
the amount of processing power required .
If an external crystal or oscillator is being used, the operating frequency can be adjusted by changing external compo-
nents . However, it could be the case that a single application can require maximum processing power at some times
and very little at others . Power-management mode allows an application to reduce its clock frequency and, therefore,
its power consumption under software control .