Maxim Integrated MAXQ610 - Manual (Page 115)

8-2
MAXQ610 User’s Guide
SECTION 8: IR TIMER
The MAXQ610 microcontroller provides a dedicated IR timer/counter module to simplify support for low-speed infrared
(IR) communication . The IR timer implements two pins (IRTX and IRRX) for supporting IR transmit and receive, respec-
tively . The IRTX pin has no corresponding port pin designation, so the standard PD, PO, and PI port control status bits
are not present . However, the IRTX pin output can be manipulated high or low using the PWCN .IRTXOUT bit when the
IRTX function is not enabled (i .e ., IREN = 0 or both IREN = 1 and IRMODE = 0) .
The IR timer is composed of two separate timing entities: a carrier generator and a carrier modulator . The carrier gen-
eration module uses the 16-bit IR carrier register (IRCA) to define the high and low time of the carrier through the IR
carrier high byte (IRCAH) and IR carrier low byte (IRCAL) . The carrier modulator uses the IR data bit (IRDATA) and IR
modulator time register (IRMT) to determine whether the carrier or the idle condition is present on IRTX .
The IR timer is enabled when the IR enable bit (IREN) is set to 1 .
The IR value register (IRV) defines the beginning value for the carrier modulator . During transmission, the IRV register
is initially loaded with the IRMT value and begins down counting towards 0000h, whereas in receive mode it counts
upward from the initial IRV value . During the receive operation, the IRV register can be configured to reload with 0000h
when capture occurs on detection of selected edges or can be allowed to continue running free throughout the receive
operation . An overflow occurs when the IR timer value rolls over from 0FFFFh to 0000h . The IR overflow flag (IROV) is
set to 1 and an interrupt is generated if enabled (IRIE = 1) .
8.1 Carrier Generation Module
The IRCAH byte defines the carrier high time in terms of the number of IR input clock, whereas the IRCAL byte defines
the carrier low time .
IR Input Clock (f
IRCLK ) = f SYS /2 IRDIV[1:0]
Carrier Frequency (f CARRIER ) = f IRCLK /(IRCAH + IRCAL + 2)
Carrier High Time = IRCAH +1
Carrier Low Time = IRCAL+1
Carrier Duty Cycle = (IRCAH +1)/(IRCAH + IRCAL + 2)
During transmission, the IRCA register is latched for each IRV down-count interval and is sampled along with the
IRTXPOL and IRDATA bits at the beginning of each new IRV down-count interval so that duty-cycle variation and fre-
quency shifting is possible from one interval to the next . This is illustrated in Figure 8-1 .
Figure 8-2 illustrates the basic carrier generation and its path to the IRTX output pin . The IR transmit polarity bit
(IRTXPOL) defines the starting/idle state and the carrier polarity of the IRTX pin when the IR timer is enabled .
8.2 IR Transmission
During IR transmission (IRMODE = 1), the carrier generator is used to create the appropriate carrier waveform, while
the necessary modulation is performed by the carrier modulator .
The carrier modulation can be performed as a function of carrier cycles or as a function of IRCLK cycles dependent on
the setting of the IRCFME bit . When IRCFME = 0, the IRV down counter is clocked by the carrier frequency and, thus,
the modulation is a function of carrier cycles . When IRCFME = 1, the IRV down counter is clocked by IRCLK, allowing
carrier modulation timing with IRCLK resolution .
The IRTXPOL bit defines the starting/idle state as well as the carrier polarity for the IRTX pin . If IRTXPOL = 1, the IRTX
pin is set to a logic-high when the IR timer module is enabled . If IRTXPOL = 0, the IRTX pin is set to a logic-low when
the IR timer is enabled .
A separate register bit, IR data (IRDATA), is used to determine whether the carrier generator output is output to the
IRTX pin for the next IRMT carrier cycles . When IRDATA = 1, the carrier waveform (or inversion of this waveform if
IRTXPOL = 1) is output on the IRTX pin during the next IRMT cycles . When IRDATA = 0, the idle condition, as defined
by IRTXPOL, is output on the IRTX pin during the next IRMT cycles .