Maxim Integrated MAXQ610 - Manual (Page 83)

5-11
MAXQ610 User’s Guide
REGISTER DESCRIPTION
PWCN.5 (IRTXOUT) IRTX Output Pin Control. This bit controls the output drive state for the IRTX pin when the
IR timer is not enabled (i .e ., IREN = 0) and when the IRTX pin has been enabled for out-
put by IRTXOE = 1 . When IREN = 0 and IRTXOE = 1, setting this bit to 1 enables a strong
output high drive on the IRTX pin . Clearing this bit to 0 enables a strong output low drive
on the IRTX pin . When IRTXOE = 0 and the IR timer is not enabled (IREN = 0), this bit con-
trols the input mode for the IRTX pin . When IRTXOE = 0, the IRTX pin is three-state . When
IRTXOE = 1, the pin is weakly pulled up .
PWCN.6 (IRRXWP) IRRX Weak Pullup Enable. This bit controls the input mode of the IRRX pin . When this bit
is set to 1, the internal weak pullup is enabled . When this bit is cleared to 0, the internal
weak pullup is turned off, resulting in the three-state input mode .
PWCN.7 (PFRST) Power-Fail Reset Flag. This bit is set to 1 whenever a power-fail reset occurs . It is unaf-
fected by other forms of reset . This bit can be checked by software following a reset to
determine if it was a power-fail reset that occurred . It should always be cleared by software
following a reset to ensure that the source of any future reset can be determined correctly .
Note that this bit is set anytime V
DD < V RST . The WDCN .POR bit can be examined to deter-
mine whether V DD was below the V P OR threshold.
PWCN.9 to PWCN.8 (PFRCK[1:0]) Power-Fail Reset Check Time Bits 1:0. These bits are used to enable duty cycling of the
V
RST power-monitoring circuitry during the time when V DD is below the V RST threshold, but
has not reached the POR threshold . The duty cycling of the power-fail monitor during the
V
RST condition is provided to reduce the time-averaged current consumption and extend
the SRAM data-retention time when the battery voltage is low, but still provide adequate
response time to exit the V
RST state if the battery source is replaced . These bits are reset
only by POR (not even V RST ) . The table below provides the bit settings and corresponding
duty cycling of the power monitor check when V
POR
< V
DD
< V
RST
.
PFRCK[1:0]
POWER-FAIL MONITOR CHECK INTERVAL (NANOPOWER RING
OSCILLATOR CYCLES)
00 No interval defined (Monitor on always as normal)
01 2 10 (~128ms for 8kHz nanopower ring oscillator frequency)
10 2 11 (~256ms for 8kHz nanopower ring oscillator frequency)
11 2 12 (~512ms for 8kHz nanopower ring oscillator frequency)
PWCN.15 to PWCN.10 Reserved . Read returns 0 .
PD4 (10h, 01h)
Port 4 Direction Register
Initialization: This register is cleared to 00h on all resets except power-fail reset . This register is unaf-
fected by power-fail reset .
Read/Write Access: Unrestricted read/write .
PD4.5 to PD4.0 Port 4 Direction Register Bits 5:0. PD4 is used to determine the direction of the port 4
function . The port pins are independently controlled by their direction bit . When a bit is set
to 1, its corresponding pin is used as an output; data in the PO register is driven on the pin .
When a bit is cleared to 0, its corresponding pin is used as an input, and allows an external
signal to drive the pin . Note that each port pin has a weak pullup circuit when functioning
as an input and the p-channel pullup transistor is controlled by its respective PO bits . If the
PO bit is set to 1, the weak pullup is on, if the PO bit is cleared to 0, the weak pullup is off
and forces the port pin into three-state .
PD4.7 to PD4.6 Reserved . Reads return 0 .
TB0R (00h, 02h) Timer B 0 Capture/Reload Value Register (16-bit register)
Initialization: This register is cleared to 0000h on all forms of reset .
Read/Write Access: Unrestricted read/write .
TB0R.15 to TB0R.0 Timer B Capture/Reload Bits 15:0. This register is used to capture the TBV value when
Timer B is configured in capture mode . This register is also used as the 16-bit reload value
when Timer B is configured in autoreload mode .