Clear-Com HX System Frames - Manual (Page 156)

3. Run TeraTerm. Configure the serial settings to the following:
Serial setting Setting
Baud rate 57600
Parity None
Data Bits 8
Stop Bits 1
Flow Control None
Table 45: Tera Term serial settings
4. Reset or power-cycle the module.
5. At this point, the procedure varies depending on whether or not an FPGA image is already
present.
If there is an FPGA image present:
a. After the reset, the following output will be shown in the TeraTerm window:
Figure 113: AES-6 FPGA upgrade using Tera Term
149 Eclipse HX Upgrade Guide