AMETEK Lx Series II Programming Manual User Manual
Page 125

Programming Manual
Lx \ Ls Series II
121
This command controls the automatic clearing at power-on of the Service Request Enable and the
Standard Event Status Enable registers (see chapter 7 under Programming the Status and Event
Registers for register details):
*PSC ON | 1
prevents the register contents from being saved causing them to be cleared
at power-on. This prevents a PON event from generating SRQ at power-
on.
PSC OFF | 0
saves the contents of the Standard Event Enable and Service Request
Enable registers in nonvolatile memory and recalls them at power-on. This
allows a PON event to generate SRQ at power-on.
Command Syntax
*PSC
Parameters
0 | 1 | OFF | ON
Example
*PSC 0 *PSC 1
Query Syntax
*PSC?
Returned Parameters
0 | 1
Related Commands
*ESE
*SRE
5.7
*RCL
Warning
Recalling a previously stored state may place hazardous voltages at the AC
source output.
This command restores the AC source to a state that was previously stored in memory with a
*SAV command to the specified location. All states are recalled with the following exceptions:
CAL:STATe is set to OFF
the trigger system is set to the Idle state by an implied ABORt command (this cancels any
uncompleted trigger actions)
The device state stored in location 0 is automatically recalled at power turn-on when the
OUTPut:PON:STATE is set to RCL0. This register only saves steady state setting, not the
transient list data. All other registers (1-15) saved both the steady state settings and the transient
list data record.
Command Syntax
*RCL
Parameters
0 through 15
Example
*RCL 3
Related Commands
*PSC *RST
*SAV
Note that recalling settings and transient list information from non-volatile memory takes some
amount of time as shown in the table below. If you develop a test program that uses the *RCL or
*SAV commands, insert the amount of delay shown in the table before sending the next command
in your program.
Command:
*RCL 0
*RCL n (n = 1 to 15)
*SAV 0
*SAV n (n = 1 to 15)
Execution time:
20 msec
40 msec
80 msec
40 msec