AMETEK Lx Series II Programming Manual - Manual (Page 123)

Programming Manual Lx \ Ls Series II
119
5.1 *CLS
This command clears the following registers (see chapter 7 under Programming the Status and
Event Registers for descriptions of all registers):
Standard Event Status
Operation Status Event
Questionable Status Event
Status Byte
Error Queue
Command Syntax *CLS
Parameters None
*ESE
This command programs the Standard Event Status Enable register bits. The programming
determines which events of the Standard Event Status Event register (see *ESR?) are allowed to
set the ESB (Event Summary Bit) of the Status Byte register. A "1" in the bit position enables the
corresponding event. All of the enabled events of the Standard Event Status Event Register are
logically ORed to cause the Event Summary Bit (ESB) of the Status Byte Register to be set. See
section 7.5 for descriptions of the Standard Event Status registers.
The query reads the Standard Event Status Enable register.
Bit Position 7 6 5 4 3 2 1 0
Bit Name PON not used CME EXE DDE QYE not used OPC
Bit Weight 128 32 16 8 4 1
Table 5-1: Bit Configuration of Standard Event Status Enable Register
CME Command error DDE Device-dependent error
EXE Execution error OPC Operation complete
PON Power-on QYE Query error
Command Syntax *ESE
Parameters 0 - 255
Power-On Value (See *PSC)
Example *ESE 129
Query Syntax *ESE?
Returned Parameters (Register value)
Related Commands *ESR? *PSC *STB?
5.2 *ESR?
This query reads the Standard Event Status Event register. Reading the register clears it. The bit
configuration of this register is the same as the Standard Event Status Enable register (see
*ESE). See section 7.5 for a detailed explanation of this register.