AMETEK Lx Series II Programming Manual - Manual (Page 103)

Programming Manual Lx \ Ls Series II
99
Bit Position 15-9 8 7-6 5 4-1 0
WTG Interface is waiting for a trigger.
CV Output voltage is regulated.
Table 4-3: Bit Configuration of Status Operation Registers
STATus:OPERation?
This query returns the value of the Operation Event register. The Event register is a read-only
register which holds (latches) all events that are passed by the Operation NTR and/or PTR filter.
Reading the Operation Event register clears it.
Query Syntax STATus:OPERation[:EVENt]?
Parameters None
Returned Parameters (Register Value)
Examples STAT:OPER:EVEN?
Related Commands *CLS STAT:OPER:NTR STAT:OPER:PTR
STATus:OPERation:CONDition?
This query returns the value of the Operation Condition register. This is a read-only register which
holds the real-time (unlatched) operational status of the Lx\Ls Series.
Query Syntax STATus:OPERation:CONDition?
Parameters None
Examples STAT:OPER:COND?
Returned Parameters (Register value)
STATus:OPERation:ENABle
This command and its query set and read the value of the Operation Enable register. This register
is a mask for enabling specific bits from the Operation Event register to set the operation
summary bit (OPER) of the Status Byte register. The operation summary bit is the logical OR of all
enabled Operation Event register bits.
Command Syntax STATus:OPERation:ENABle
Parameters 0 to 32727
Default Value 0
Examples STAT:OPER:ENAB 32
STAT:OPER:ENAB 1
Query Syntax STATus:OPERation:ENABle?
Returned Parameters (Register value)
Related Commands STAT:OPER:EVEN
STATus:OPERation:NTR STATus:OPERation:PTR
These commands set or read the value of the Operation NTR (Negative-Transition) and PTR
(Positive-Transition) registers. These registers serve as polarity filters between the Operation
Enable and Operation Event registers to cause the following actions:
When a bit in the Operation NTR register is set to 1, then a 1-to-0 transition of the
corresponding bit in the Operation Condition register causes that bit in the Operation Event
register to be set.
When a bit of the Operation PTR register is set to 1, then a 0-to-1 transition of the
corresponding bit in the Operation Condition register causes that bit in the Operation Event
register to be set.