Intel IA-32 User Manual

Ia-32 intel, Architecture software developer’s manual, Volume 3a: system programming guide, part 1

Table of contents

Document Outline

IA-32 Intel® Architecture Software Developer’s Manual
Disclaimer
CONTENTS FOR VOLUME 3A AND 3B
CHAPTER 1 About This Manual
- 1.1 IA-32 Processors Covered in this Manual
- 1.2 Overview of The SYSTEM PROGRAMMING GUIDE
- 1.3 Notational Conventions
- 1.4 Related Literature
CHAPTER 2 System Architecture Overview
- 2.1 Overview of the System-Level Architecture
- 2.2 Modes of Operation
- 2.3 System Flags and Fields in the EFLAGS Register
  - 2.3.1 System Flags and Fields in IA-32e Mode
- 2.4 Memory-Management Registers
- 2.5 Control Registers
  - 2.5.1 CPUID Qualification of Control Register Flags
- 2.6 System Instruction Summary
CHAPTER 3 Protected-Mode Memory Management
- 3.1 Memory Management Overview
- 3.2 Using Segments
- 3.3 Physical Address Space
  - 3.3.1 Physical Address Space for Processors with Intel® EM64T
- 3.4 Logical and Linear Addresses
- 3.5 System Descriptor Types
  - 3.5.1 Segment Descriptor Tables
  - 3.5.2 Segment Descriptor Tables in IA-32e Mode
- 3.6 Paging (Virtual Memory) Overview
  - 3.6.1 Paging Options
  - 3.6.2 Page Tables and Directories in the Absence of Intel EM64T
- 3.7 Page Translation using 32-Bit Physical Addressing
- 3.8 36-Bit Physical Addressing Using the PAE Paging Mechanism
- 3.9 36-Bit Physical Addressing Using the PSE-36 Paging Mechanism
- 3.10 PAE-Enabled Paging in IA-32e Mode
- 3.11 Mapping Segments to Pages
- 3.12 Translation Lookaside Buffers (TLBs)
CHAPTER 4 Protection
- 4.1 Enabling and Disabling Segment and Page Protection
- 4.2 Fields and Flags Used for Segment-Level and Page-Level Protection
  - 4.2.1 Code Segment Descriptor in 64-bit Mode
- 4.3 Limit Checking
  - 4.3.1 Limit Checking in 64-bit Mode
- 4.4 Type Checking
  - 4.4.1 Null Segment Selector Checking
    - 4.4.1.1 NULL Segment Checking in 64-bit Mode
- 4.5 Privilege Levels
- 4.6 Privilege Level Checking When Accessing Data Segments
  - 4.6.1 Accessing Data in Code Segments
- 4.7 Privilege Level Checking When Loading the SS Register
- 4.8 Privilege Level Checking When Transferring Program Control Between Code Segments
- 4.9 Privileged Instructions
- 4.10 Pointer Validation
- 4.11 Page-Level Protection
- 4.12 Combining Page and Segment Protection
- 4.13 Page-Level Protection and Execute-Disable Bit
CHAPTER 5 Interrupt and Exception Handling
- 5.1 Interrupt and Exception Overview
- 5.2 Exception and Interrupt Vectors
- 5.3 Sources of Interrupts
- 5.4 Sources of Exceptions
- 5.5 Exception Classifications
- 5.6 Program or Task Restart
- 5.7 NonMaskable Interrupt (NMI)
  - 5.7.1 Handling Multiple NMIs
- 5.8 Enabling and Disabling Interrupts
- 5.9 Priority Among Simultaneous Exceptions and Interrupts
- 5.10 Interrupt Descriptor Table (IDT)
- 5.11 IDT Descriptors
- 5.12 Exception and Interrupt Handling
  - 5.12.1 Exception- or Interrupt-Handler Procedures
    - 5.12.1.1 Protection of Exception- and Interrupt-Handler Procedures
    - 5.12.1.2 Flag Usage By Exception- or Interrupt-Handler Procedure
  - 5.12.2 Interrupt Tasks
- 5.13 Error Code
- 5.14 Exception and Interrupt Handling in 64-bit Mode
- 5.15 Exception and Interrupt Reference
CHAPTER 6 Task Management
- 6.1 Task Management Overview
- 6.2 Task Management Data Structures
- 6.3 Task Switching
- 6.4 Task Linking
  - 6.4.1 Use of Busy Flag To Prevent Recursive Task Switching
  - 6.4.2 Modifying Task Linkages
- 6.5 Task Address Space
  - 6.5.1 Mapping Tasks to the Linear and Physical Address Spaces
  - 6.5.2 Task Logical Address Space
- 6.6 16-Bit Task-State Segment (TSS)
- 6.7 Task Management in 64-bit Mode
CHAPTER 7 Multiple-Processor Management
- 7.1 Locked Atomic Operations
- 7.2 Memory Ordering
- 7.3 Propagation of Page Table and Page Directory Entry Changes to Multiple Processors
- 7.4 Serializing Instructions
- 7.5 Multiple-Processor (MP) Initialization
- 7.6 Hyper-Threading and Multi-Core Technology
- 7.7 Detecting Hardware Multi-Threading Support and Topology
- 7.8 Intel® Hyper-Threading Technology Architecture
- 7.9 Dual-Core Architecture
- 7.10 Programming Considerations for Hardware Multi-Threading Capable Processors
- 7.11 Management of Idle and Blocked Conditions
CHAPTER 8 Advanced Programmable Interrupt Controller (APIC)
- 8.1 Local and I/O APIC Overview
- 8.2 System Bus Vs. APIC Bus
- 8.3 the Intel® 82489DX External APIC, The APIC, and the xAPIC
- 8.4 Local APIC
- 8.5 Handling Local Interrupts
- 8.6 Issuing Interprocessor Interrupts
- 8.7 System and APIC Bus Arbitration
- 8.8 Handling Interrupts
- 8.9 Spurious Interrupt
- 8.10 APIC Bus Message Passing Mechanism and Protocol (P6 Family, Pentium Processors)
  - 8.10.1 Bus Message Formats
- 8.11 Message Signalled Interrupts
  - 8.11.1 Message Address Register Format
  - 8.11.2 Message Data Register Format
CHAPTER 9 Processor Management and Initialization
- 9.1 Initialization Overview
- 9.2 x87 FPU Initialization
  - 9.2.1 Configuring the x87 FPU Environment
  - 9.2.2 Setting the Processor for x87 FPU Software Emulation
- 9.3 Cache Enabling
- 9.4 Model-Specific Registers (MSRs)
- 9.5 Memory Type Range Registers (MTRRs)
- 9.6 Initializing SSE/SSE2/SSE3 Extensions
- 9.7 Software Initialization for Real-Address Mode Operation
  - 9.7.1 Real-Address Mode IDT
  - 9.7.2 NMI Interrupt Handling
- 9.8 Software Initialization for Protected-Mode Operation
- 9.9 Mode Switching
  - 9.9.1 Switching to Protected Mode
  - 9.9.2 Switching Back to Real-Address Mode
- 9.10 Initialization and Mode Switching Example
- 9.11 Microcode Update Facilities
CHAPTER 10 Memory Cache Control
- 10.1 Internal Caches, TLBs, and Buffers
- 10.2 Caching Terminology
- 10.3 Methods of Caching Available
  - 10.3.1 Buffering of Write Combining Memory Locations
  - 10.3.2 Choosing a Memory Type
- 10.4 Cache Control Protocol
- 10.5 Cache Control
- 10.6 Self-Modifying Code
- 10.7 Implicit Caching (Pentium 4, Intel Xeon, and P6 Family Processors)
- 10.8 Explicit Caching
- 10.9 Invalidating the Translation Lookaside Buffers (TLBs)
- 10.10 Store Buffer
- 10.11 Memory Type Range Registers (MTRRs)
- 10.12 Page Attribute Table (PAT)
CHAPTER 11 Intel® MMX™ Technology System Programming
- 11.1 Emulation of the MMX Instruction Set
- 11.2 The MMX State and MMX Register Aliasing
  - 11.2.1 Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag Word
- 11.3 Saving and Restoring the MMX State and Registers
- 11.4 Saving MMX State on Task or Context Switches
- 11.5. EXCEPTIONS That Can Occur When Executing MMX Instructions
  - 11.5.1 Effect of MMX Instructions on Pending x87 Floating-Point Exceptions
- 11.6 Debugging MMX Code
CHAPTER 12 SSE, SSE2 and SSE3 System Programming
- 12.1 Providing Operating System Support for SSE/SSE2/SSE3 Extensions
- 12.2 Emulation of SSE/SSE2/SSE3 Extensions
- 12.3 Saving and Restoring the SSE/SSE2/SSE3 State
- 12.4 Saving the SSE/SSE2/SSE3 State on Task or Context Switches
- 12.5 Designing OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and SSE/SSE2/SSE3 state on Task or Context Switches
  - 12.5.1. Using the TS Flag to Control the Saving of the x87 FPU, MMX, SSE, SSE2 and SSE3 State
CHAPTER 13 Power and Thermal Management
- 13.1 Enhanced Intel Speedstep® Technology
  - 13.1.1 Software Interface For Initiating Performance State Transitions
- 13.2 P-State Hardware Coordination
- 13.3 MWAIT Extensions for Advanced Power Management
- 13.4 Thermal Monitoring and Protection
CHAPTER 14 Machine-Check Architecture
- 14.1 Machine-Check Exceptions and Architecture
- 14.2 Compatibility with Pentium Processor
- 14.3 Machine-Check MSRs
- 14.4 Machine-Check Availability
- 14.5 Machine-Check Initialization
- 14.6. Interpreting the MCA Error Codes
- 14.7 Guidelines for Writing Machine-Check Software
CHAPTER 15 8086 Emulation
- 15.1 Real-Address Mode
- 15.2 Virtual-8086 Mode
- 15.3 Interrupt and Exception Handling in Virtual-8086 Mode
- 15.4 Protected-Mode Virtual Interrupts
CHAPTER 16 Mixing 16-Bit and 32-Bit Code
- 16.1 Defining 16-Bit and 32-Bit Program Modules
- 16.2 Mixing 16-Bit and 32-Bit Operations Within a Code Segment
- 16.3 Sharing Data Among Mixed-Size Code Segments
- 16.4 Transferring Control Among Mixed-Size Code Segments
CHAPTER 17 IA-32 Architecture Compatibility
- 17.1. IA-32 Processor Families and Categories
- 17.2. Reserved Bits
- 17.3. Enabling New Functions and Modes
- 17.4. Detecting the Presence of New Features Through Software
- 17.5. Intel MMX Technology
- 17.6. Streaming SIMD Extensions (SSE)
- 17.7. Streaming SIMD Extensions 2 (SSE2)
- 17.8. Streaming SIMD Extensions 3 (SSE3)
- 17.9. Hyper-Threading Technology
- 17.10. Dual-Core Technology
- 17.11. Specific Features of Dual-Core Processor
- 17.12. New Instructions In the Pentium and Later IA-32 Processors
  - 17.12.1 Instructions Added Prior to the Pentium Processor
- 17.13. Obsolete Instructions
- 17.14. Undefined Opcodes
- 17.15. New Flags in the EFLAGS Register
  - 17.15.1 Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors
- 17.16. Stack Operations
  - 17.16.1 PUSH SP
  - 17.16.2 EFLAGS Pushed on the Stack
- 17.17. x87 FPU
  - 17.17.1 Control Register CR0 Flags
  - 17.17.2 x87 FPU Status Word
    - 17.17.2.1 Condition Code Flags (C0 through C3)
    - 17.17.2.2 Stack Fault Flag
  - 17.17.3 x87 FPU Control Word
  - 17.17.4 x87 FPU Tag Word
  - 17.17.5 Data Types
    - 17.17.5.1 NaNs
    - 17.17.5.2 Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats
  - 17.17.6 Floating-Point Exceptions
  - 17.17.7 Changes to Floating-Point Instructions
  - 17.17.8 Transcendental Instructions
  - 17.17.9 Obsolete Instructions
  - 17.17.10 WAIT/FWAIT Prefix Differences
  - 17.17.11 Operands Split Across Segments and/or Pages
  - 17.17.12 FPU Instruction Synchronization
- 17.18. Serializing Instructions
- 17.19. FPU and Math Coprocessor Initialization
  - 17.19.1 Intel® 387 and Intel® 287 Math Coprocessor Initialization
  - 17.19.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization
- 17.20. Control Registers
- 17.21. Memory Management Facilities
  - 17.21.1 New Memory Management Control Flags
  - 17.21.2 CD and NW Cache Control Flags
  - 17.21.3 Descriptor Types and Contents
  - 17.21.4 Changes in Segment Descriptor Loads
- 17.22. Debug Facilities
  - 17.22.1 Differences in Debug Register DR6
  - 17.22.2 Differences in Debug Register DR7
  - 17.22.3 Debug Registers DR4 and DR5
- 17.23. Recognition of Breakpoints
- 17.24. Exceptions and/or Exception Conditions
  - 17.24.1 Machine-Check Architecture
  - 17.24.2 Priority OF Exceptions
- 17.25. Interrupts
  - 17.25.1 Interrupt Propagation Delay
  - 17.25.2 NMI Interrupts
  - 17.25.3 IDT Limit
- 17.26. Advanced Programmable Interrupt Controller (APIC)
  - 17.26.1 Software Visible Differences Between the Local APIC and the 82489DX
  - 17.26.2 New Features Incorporated in the Local APIC for the P6 Family and Pentium Processors
  - 17.26.3 New Features Incorporated in the Local APIC of the Pentium 4 and Intel Xeon Processors
- 17.27. Task Switching and TSs
  - 17.27.1 P6 Family and Pentium Processor TSS
  - 17.27.2 TSS Selector Writes
  - 17.27.3 Order of Reads/Writes to the TSS
  - 17.27.4 Using A 16-Bit TSS with 32-Bit Constructs
  - 17.27.5 Differences in I/O Map Base Addresses
- 17.28. Cache Management
  - 17.28.1 Self-Modifying Code with Cache Enabled
  - 17.28.2 Disabling the L3 Cache
- 17.29. Paging
  - 17.29.1 Large Pages
  - 17.29.2 PCD and PWT Flags
  - 17.29.3 Enabling and Disabling Paging
- 17.30. Stack Operations
  - 17.30.1 Selector Pushes and Pops
  - 17.30.2 Error Code Pushes
  - 17.30.3 Fault Handling Effects on the Stack
  - 17.30.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate
- 17.31. Mixing 16- and 32-Bit Segments
- 17.32. Segment and Address Wraparound
  - 17.32.1 Segment Wraparound
- 17.33. Store Buffers and Memory Ordering
- 17.34. Bus Locking
- 17.35. Bus Hold
- 17.36. Model-Specific Extensions to the IA-32
  - 17.36.1 Model-Specific Registers
  - 17.36.2 RDMSR and WRMSR Instructions
  - 17.36.3 Memory Type Range Registers
  - 17.36.4 Machine-Check Exception and Architecture
  - 17.36.5 Performance-Monitoring Counters
- 17.37. Two Ways to Run Intel 286 Processor Tasks