Intel IA-32 - Manual (Page 384)

9-10 Vol. 3A
PROCESSOR MANAGEMENT AND INITIALIZATION
9.6 INITIALIZING SSE/SSE2/SSE3 EXTENSIONS
For processors that contain SSE/SSE2/SSE3 extensions, steps must be taken when initializing
the processor to allow execution of these instructions.
1. Check the CPUID feature flags for the presence of the SSE/SSE2/SSE3 extensions
(respectively: EDX bits 25 and 26, ECX bit 0) and support for the FXSAVE and
FXRSTOR instructions (EDX bit 24). Also check for support for the CLFLUSH
instruction (EDX bit 19). The CPUID feature flags are loaded in the EDX and ECX
registers when the CPUID instruction is executed with a 1 in the EAX register.
2. Set the OSFXSR flag (bit 9 in control register CR4) to indicate that the operating system
supports saving and restoring the SSE/SSE2/SSE3 execution environment (XXM and
MXCSR registers) with the FXSAVE and FXRSTOR instructions, respectively. See
Section 2.5, “Control Registers,” for a description of the OSFXSR flag.
3. Set the OSXMMEXCPT flag (bit 10 in control register CR4) to indicate that the operating
system supports the handling of SSE/SSE2/SSE3 SIMD floating-point exceptions (#XF).
See Section 2.5, “Control Registers,” for a description of the OSXMMEXCPT flag.
4. Set the mask bits and flags in the MXCSR register according to the mode of operation
desired for SSE/SSE2/SSE3 SIMD floating-point instructions. See “MXCSR Control and
Status Register” in Chapter 10, “Programming with Streaming SIMD Extensions (SSE),”
of the IA-32 Intel® Architecture Software Developer’s Manual, Volume 1, for a detailed
description of the bits and flags in the MXCSR register.
9.7 SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE
OPERATION
Following a hardware reset (either through a power-up or the assertion of the RESET# pin) the
processor is placed in real-address mode and begins executing software initialization code from
physical address FFFFFFF0H. Software initialization code must first set up the necessary data
structures for handling basic system functions, such as a real-mode IDT for handling interrupts
and exceptions. If the processor is to remain in real-address mode, software must then load addi-
tional operating-system or executive code modules and data structures to allow reliable execu-
tion of application programs in real-address mode.
If the processor is going to operate in protected mode, software must load the necessary data
structures to operate in protected mode and then switch to protected mode. The protected-mode
data structures that must be loaded are described in Section 9.8, “Software Initialization for
Protected-Mode Operation.”