Intel IA-32 - Manual (Page 622)

17-30 Vol. 3A
IA-32 ARCHITECTURE COMPATIBILITY
17.27.1 P6 Family and Pentium Processor TSS
When the virtual mode extensions are enabled (by setting the VME flag in control register CR4),
the TSS in the P6 family and Pentium processors contain an interrupt redirection bit map, which
is used in virtual-8086 mode to redirect interrupts back to an 8086 program.
17.27.2 TSS Selector Writes
During task state saves, the Intel486 processor writes 2-byte segment selectors into a 32-bit TSS,
leaving the upper 16 bits undefined. For performance reasons, the P6 family and Pentium
processors write 4-byte segment selectors into the TSS, with the upper 2 bytes being 0. For
compatibility reasons, code should not depend on the value of the upper 16 bits of the selector
in the TSS.
17.27.3 Order of Reads/Writes to the TSS
The order of reads and writes into the TSS is processor dependent. The P6 family and Pentium
processors may generate different page-fault addresses in control register CR2 in the same TSS
area than the Intel486 and Intel386 processors, if a TSS crosses a page boundary (which is not
recommended).
17.27.4 Using A 16-Bit TSS with 32-Bit Constructs
Task switches using 16-bit TSSs should be used only for pure 16-bit code. Any new code written
using 32-bit constructs (operands, addressing, or the upper word of the EFLAGS register)
should use only 32-bit TSSs. This is due to the fact that the 32-bit processors do not save the
upper 16 bits of EFLAGS to a 16-bit TSS. A task switch back to a 16-bit task that was executing
in virtual mode will never re-enable the virtual mode, as this flag was not saved in the upper half
of the EFLAGS value in the TSS. Therefore, it is strongly recommended that any code using
32-bit constructs use a 32-bit TSS to ensure correct behavior in a multitasking environment.
17.27.5 Differences in I/O Map Base Addresses
The Intel486 processor considers the TSS segment to be a 16-bit segment and wraps around the
64K boundary. Any I/O accesses check for permission to access this I/O address at the I/O base
address plus the I/O offset. If the I/O map base address exceeds the specified limit of 0DFFFH,
an I/O access will wrap around and obtain the permission for the I/O address at an incorrect
location within the TSS. A TSS limit violation does not occur in this situation on the Intel486
processor. However, the P6 family and Pentium processors consider the TSS to be a 32-bit
segment and a limit violation occurs when the I/O base address plus the I/O offset is greater than
the TSS limit. By following the recommended specification for the I/O base address to be less
than 0DFFFH, the Intel486 processor will not wrap around and access incorrect locations within
the TSS for I/O port validation and the P6 family and Pentium processors will not experience