Intel IA-32 - Manual (Page 613)

Vol. 3A 17-21
IA-32 ARCHITECTURE COMPATIBILITY
cmp ax, 037fh
jz Intel487_SX_Math_CoProcessor_present;ax=037fh
jmp Intel486_SX_microprocessor_present;ax=ffffh
If the Intel 487 SX math coprocessor is not present, the following code can be run to set the CR0
register for the Intel486 SX processor.
mov eax, cr0
and eax, fffffffdh ;make MP=0
or eax, 0024h ;make EM=1, NE=1
mov cr0, eax
This initialization will cause any floating-point instruction to generate a device not available
exception (#NH), interrupt 7. The software emulation will then take control to execute these
instructions. This code is not required if an Intel 487 SX math coprocessor is present in the
system. In that case, the typical initialization routine for the Intel486 SX microprocessor will be
adequate.
Also, when designing an Intel486 SX processor based system with an Intel 487 SX math copro-
cessor, timing loops should be independent of clock speed and clocks per instruction. One way
to attain this is to implement these loops in hardware and not in software (for example, BIOS).
17.20. CONTROL REGISTERS
The following sections identify the new control registers and control register flags and fields that
were introduced to the 32-bit IA-32 in various processor families. See Figure 2-6 for the location
of these flags and fields in the control registers.
The Pentium III processor introduced one new control flag in control register CR4:
•
OSXMMEXCPT (bit 10) — The OS will set this bit if it supports unmasked SIMD
floating-point exceptions.
The Pentium II processor introduced one new control flag in control register CR4:
•
OSFXSR (bit 9) — The OS supports saving and restoring the Pentium III processor state
during context switches.
The Pentium Pro processor introduced three new control flags in control register CR4:
•
PAE (bit 5) — Physical address extension. Enables paging mechanism to reference 36-bit
physical addresses when set; restricts physical addresses to 32 bits when clear (see also:
Section 17.21.1.1, “Physical Memory Addressing Extension”).
•
PGE (bit 7) — Page global enable. Inhibits flushing of frequently-used or shared pages on
task switches (see also: Section 17.21.1.2, “Global Pages”).
•
PCE (bit 8) — Performance-monitoring counter enable. Enables execution of the RDPMC
instruction at any protection level.