Intel IA-32 - Manual (Page 556)

15-6 Vol. 3A
8086 EMULATION
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ENTER and LEAVE control instructions.
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BOUND instruction.
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CPU identification (CPUID) instruction.
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System instructions CLTS, INVD, WINVD, INVLPG, LGDT, SGDT, LIDT, SIDT,
LMSW, SMSW, RDMSR, WRMSR, RDTSC, and RDPMC.
Execution of any of the other IA-32 architecture instructions (not given in the previous two lists)
in real-address mode result in an invalid-opcode exception (#UD) being generated.
15.1.4 Interrupt and Exception Handling
When operating in real-address mode, software must provide interrupt and exception-handling
facilities that are separate from those provided in protected mode. Even during the early stages
of processor initialization when the processor is still in real-address mode, elementary real-
address mode interrupt and exception-handling facilities must be provided to insure reliable
operation of the processor, or the initialization code must insure that no interrupts or exceptions
will occur.
The IA-32 processors handle interrupts and exceptions in real-address mode similar to the way
they handle them in protected mode. When a processor receives an interrupt or generates an
exception, it uses the vector number of the interrupt or exception as an index into the interrupt
table. (In protected mode, the interrupt table is called the interrupt descriptor table (IDT), but
in real-address mode, the table is usually called the interrupt vector table, or simply the inter-
rupt table.) The entry in the interrupt vector table provides a pointer to an interrupt- or excep-
tion-handler procedure. (The pointer consists of a segment selector for a code segment and a
16-bit offset into the segment.) The processor performs the following actions to make an
implicit call to the selected handler:
1. Pushes the current values of the CS and EIP registers onto the stack. (Only the 16 least-
significant bits of the EIP register are pushed.)
2. Pushes the low-order 16 bits of the EFLAGS register onto the stack.
3. Clears the IF flag in the EFLAGS register to disable interrupts.
4. Clears the TF, RC, and AC flags, in the EFLAGS register.
5. Transfers program control to the location specified in the interrupt vector table.
An IRET instruction at the end of the handler procedure reverses these steps to return program
control to the interrupted program. Exceptions do not return error codes in real-address mode.
The interrupt vector table is an array of 4-byte entries (see Figure 15-2). Each entry consists of
a far pointer to a handler procedure, made up of a segment selector and an offset. The processor
scales the interrupt or exception vector by 4 to obtain an offset into the interrupt table. Following
reset, the base of the interrupt vector table is located at physical address 0 and its limit is set to
3FFH. In the Intel 8086 processor, the base address and limit of the interrupt vector table cannot
be changed. In the later IA-32 processors, the base address and limit of the interrupt vector table
are contained in the IDTR register and can be changed using the LIDT instruction.