Intel IA-32 - Manual (Page 184)

5-8 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
5.7 NONMASKABLE INTERRUPT (NMI)
The nonmaskable interrupt (NMI) can be generated in either of two ways:
•
External hardware asserts the NMI pin.
•
The processor receives a message on the system bus (Pentium 4 and Intel Xeon processors)
or the APIC serial bus (P6 family and Pentium processors) with a delivery mode NMI.
When the processor receives a NMI from either of these sources, the processor handles it imme-
diately by calling the NMI handler pointed to by interrupt vector number 2. The processor also
invokes certain hardware conditions to insure that no other interrupts, including NMI interrupts,
are received until the NMI handler has completed executing (see Section 5.7.1, “Handling
Multiple NMIs”).
Also, when an NMI is received from either of the above sources, it cannot be masked by the IF
flag in the EFLAGS register.
It is possible to issue a maskable hardware interrupt (through the INTR pin) to vector 2 to invoke
the NMI interrupt handler; however, this interrupt will not truly be an NMI interrupt. A true NMI
interrupt that activates the processor’s NMI-handling hardware can only be delivered through
one of the mechanisms listed above.
5.7.1 Handling Multiple NMIs
While an NMI interrupt handler is executing, the processor disables additional calls to the NMI
handler until the next IRET instruction is executed. This blocking of subsequent NMIs prevents
stacking up calls to the NMI handler. It is recommended that the NMI interrupt handler be
accessed through an interrupt gate to disable maskable hardware interrupts (see Section 5.8.1,
“Masking Maskable Hardware Interrupts”). If the NMI handler is a virtual-8086 task with an
IOPL of less than 3, an IRET instruction issued from the handler generates a general-protection
exception (see Section 15.2.7, “Sensitive Instructions”). In this case, the NMI is unmasked
before the general-protection exception handler is invoked.
5.8 ENABLING AND DISABLING INTERRUPTS
The processor inhibits the generation of some interrupts, depending on the state of the processor
and of the IF and RF flags in the EFLAGS register, as described in the following sections.