Intel IA-32 - Manual (Page 127)

Vol. 3A 3-47
PROTECTED-MODE MEMORY MANAGEMENT
•
Implicitly by executing a task switch, which automatically changes the contents of the CR3
register.
The INVLPG instruction is provided to invalidate a specific page-table entry in the TLB.
Normally, this instruction invalidates only an individual TLB entry; however, in some cases, it
may invalidate more than the selected entry and may even invalidate all of the TLBs. This
instruction ignores the setting of the G flag in a page-directory or page-table entry (see following
paragraph).
(Introduced in the Pentium Pro processor.) The page global enable (PGE) flag in register CR4
and the global (G) flag of a page-directory or page-table entry (bit 8) can be used to prevent
frequently used pages from being automatically invalidated in the TLBs on a task switch or a
load of register CR3. (See Section 3.7.6, “Page-Directory and Page-Table Entries”, for more
information about the global flag.) When the processor loads a page-directory or page-table
entry for a global page into a TLB, the entry will remain in the TLB indefinitely. The only ways
to deterministically invalidate global page entries are as follows:
•
Clear the PGE flag; this will invalidate the TLBs.
•
Execute the INVLPG instruction to invalidate individual page-directory or page-table
entries in the TLBs.
For additional information about invalidation of the TLBs, see Section 10.9, “Invalidating the
Translation Lookaside Buffers (TLBs)”.