Intel IA-32 - Manual (Page 504)

12-6 Vol. 3A
SSE, SSE2 AND SSE3 SYSTEM PROGRAMMING
same conditions that cause x87 FPU floating-point error exceptions (#MF) to be generated for
x87 FPU instructions.
Each of these exceptions can be masked, in which case the processor returns a reasonable result
to the destination operand without invoking an exception handler. However, if any of these
exceptions are left unmasked, detection of the exception condition results in a SIMD floating-
point exception (#XF) being generated. See Chapter 5, “Interrupt 19—SIMD Floating-Point
Exception (#XF).”
To handle unmasked SIMD floating-point exceptions, the operating system or executive must
provide an exception handler. The section titled “SSE and SSE2 SIMD Floating-Point Excep-
tions” in Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE3),” of the IA-32
Intel® Architecture Software Developer’s Manual, Volume 1, describes the SIMD floating-point
exception classes and gives suggestions for writing an exception handler to handle them.
To indicate that the operating system provides a handler for SIMD floating-point exceptions
(#XF), the OSXMMEXCPT flag (bit 10) must be set in control register CR0.
12.1.6.1 Numeric Error flag and IGNNE#
SSE/SSE2/SSE3 extensions ignore the NE flag in control register CR0 (that is, treats it as if it
were always set) and the IGNNE# pin. When an unmasked SIMD floating-point exception is
detected, it is always reported by generating a SIMD floating-point exception (#XF).
12.2 EMULATION OF SSE/SSE2/SSE3 EXTENSIONS
The IA-32 architecture does not support emulation of the SSE/SSE2/SSE3 instructions, as it
does for x87 FPU instructions. The EM flag in control register CR0 (provided to invoke emula-
tion of x87 FPU instructions) cannot be used to invoke emulation of SSE/SSE2/SSE3 instruc-
tions. If an SSE/SSE2/SSE3 instruction is executed when the EM flag is set, an invalid opcode
exception (#UD) is generated (see Table 12-1).
12.3 SAVING AND RESTORING THE SSE/SSE2/SSE3 STATE
The SSE/SSE2/SSE3 state consists of the state of the XMM and MXCSR registers. The recom-
mended method of saving and restoring this state follows:
•
Execute an FXSAVE instruction to save the state of the XMM and MXCSR registers to
memory.
•
Execute an FXRSTOR instruction to restore the state of the XMM and MXCSR registers
from the image saved in memory by the FXSAVE instruction.
This save and restore method is required for operating systems (see Section 12.5, “Designing
OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and SSE/SSE2/SSE3 state on
Task or Context Switches”).