Intel IA-32 - Manual (Page 180)

5-4 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
The processor’s local APIC is normally connected to a system-based I/O APIC. Here, external
interrupts received at the I/O APIC’s pins can be directed to the local APIC through the system
bus (Pentium 4 and Intel Xeon processors) or the APIC serial bus (P6 family and Pentium
processors). The I/O APIC determines the vector number of the interrupt and sends this number
to the local APIC. When a system contains multiple processors, processors can also send inter-
rupts to one another by means of the system bus (Pentium 4 and Intel Xeon processors) or the
APIC serial bus (P6 family and Pentium processors).
The LINT[1:0] pins are not available on the Intel486 processor and earlier Pentium processors
that do not contain an on-chip local APIC. These processors have dedicated NMI and INTR
pins. With these processors, external interrupts are typically generated by a system-based inter-
rupt controller (8259A), with the interrupts being signaled through the INTR pin.
Note that several other pins on the processor can cause a processor interrupt to occur. However,
these interrupts are not handled by the interrupt and exception mechanism described in this
chapter. These pins include the RESET#, FLUSH#, STPCLK#, SMI#, R/S#, and INIT# pins.
The pins are included on a particular IA-32 processor is implementation dependent. The func-
tions of these pins are described in the data books for the individual processors. The SMI# pin
is described in Chapter 24, “System Management.”
5.3.2 Maskable Hardware Interrupts
Any external interrupt that is delivered to the processor by means of the INTR pin or through
the local APIC is called a maskable hardware interrupt. Maskable hardware interrupts that can
be delivered through the INTR pin include all IA-32 architecture defined interrupt vectors from
0 through 255; those that can be delivered through the local APIC include interrupt vectors 16
through 255.
The IF flag in the EFLAGS register permits all maskable hardware interrupts to be masked as a
group (see Section 5.8.1, “Masking Maskable Hardware Interrupts”). Note that when interrupts
0 through 15 are delivered through the local APIC, the APIC indicates the receipt of an illegal
vector.
5.3.3 Software-Generated Interrupts
The INT n instruction permits interrupts to be generated from within software by supplying an
interrupt vector number as an operand. For example, the INT 35 instruction forces an implicit
call to the interrupt handler for interrupt 35.
Any of the interrupt vectors from 0 to 255 can be used as a parameter in this instruction. If the
processor’s predefined NMI vector is used, however, the response of the processor will not be
the same as it would be from an NMI interrupt generated in the normal manner. If vector number
2 (the NMI vector) is used in this instruction, the NMI interrupt handler is called, but the
processor’s NMI-handling hardware is not activated.
Interrupts generated in software with the INT n instruction cannot be masked by the IF flag in
the EFLAGS register.