Intel IA-32 - Manual (Page 55)

Vol. 3A 2-7
SYSTEM ARCHITECTURE OVERVIEW
A task can also be accessed through a task gate. A task gate is similar to a call gate, except that
it provides access (through a segment selector) to a TSS rather than a code segment.
2.1.3.1 Task-State Segments in IA-32e Mode
Hardware task switches are not supported in IA-32e mode. However, TSSs continue to exist.
The base address of a TSS is specified by its descriptor.
A 64-bit TSS holds the following information that is important to 64-bit operation:
•
Stack pointer addresses for each privilege level
•
Pointer addresses for the interrupt stack table
•
Offset address of the IO-permission bitmap (from the TSS base)
The task register is expanded to hold 64-bit base addresses in IA-32e mode. See also: Section 6.7,
“Task Management in 64-bit Mode.”
2.1.4 Interrupt and Exception Handling
External interrupts, software interrupts and exceptions are handled through the interrupt
descriptor table (IDT). The IDT stores a collection of gate descriptors that provide access to
interrupt and exception handlers. Like the GDT, the IDT is not a segment. The linear address for
the base of the IDT is contained in the IDT register (IDTR).
Gate descriptors in the IDT can be interrupt, trap, or task gate descriptors. To access an interrupt
or exception handler, the processor first receives an interrupt vector (interrupt number) from
internal hardware, an external interrupt controller, or from software by means of an INT, INTO,
INT 3, or BOUND instruction. The interrupt vector provides an index into the IDT. If the
selected gate descriptor is an interrupt gate or a trap gate, the associated handler procedure is
accessed in a manner similar to calling a procedure through a call gate. If the descriptor is a task
gate, the handler is accessed through a task switch.
2.1.4.1 Interrupt and Exception Handling IA-32e Mode
In IA-32e mode, interrupt descriptors are expanded to 16 bytes to support 64-bit base addresses.
This is true for 64-bit mode and compatibility mode.
The IDTR register is expanded to hold a 64-bit base address. Task gates are not supported.
2.1.5 Memory Management
System architecture supports either direct physical addressing of memory or virtual memory
(through paging). When physical addressing is used, a linear address is treated as a physical
address. When paging is used: all code, data, stack, and system segments (including the GDT
and IDT) can be paged with only the most recently accessed pages being held in physical
memory.