Intel IA-32 - Manual (Page 470)

10-30 Vol. 3A
MEMORY CACHE CONTROL
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PhysBase field, bits 12 through (MAXPHYADDR-1) — Specifies the base address of
the address range. This 24-bit value, in the case where MAXPHYADDR is 36 bits, is
extended by 12 bits at the low end to form the base address (this automatically aligns the
address on a 4-KByte boundary).
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PhysMask field, bits 12 through (MAXPHYADDR-1) — Specifies a mask (24 bits if the
maximum physical address size is 36 bits, 28 bits if the maximum physical address size is
40 bits). The mask determines the range of the region being mapped, according to the
following relationships:
— Address_Within_Range AND PhysMask = PhysBase AND PhysMask
— This value is extended by 12 bits at the low end to form the mask value. For more
information: see Section 10.11.3, “Example Base and Mask Calculations.”
— The width of the PhysMask field depends on the maximum physical address size
supported by the processor.
CPUID.80000008H reports the maximum physical address size supported by the
processor. If CPUID.80000008H is not available, software may assume that the
processor supports a 36-bit physical address size (then PhysMask is 24 bits wide and
the upper 28 bits of IA32_MTRR_PHYSMASKn are reserved). See the Note below.
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V (valid) flag, bit 11 — Enables the register pair when set; disables register pair when
clear.