Intel IA-32 - Manual (Page 475)

Vol. 3A 10-35
MEMORY CACHE CONTROL
d. If two or more variable memory ranges match and the memory types are WT and WB,
the WT memory type is used.
e. For overlaps not defined by the above rules, processor behavior is undefined.
3. If no fixed or variable memory range matches, the processor uses the default memory type.
10.11.5 MTRR Initialization
On a hardware reset, a Pentium 4, Intel Xeon, or P6 family processor clears the valid flags in the
variable-range MTRRs and clears the E flag in the IA32_MTRR_DEF_TYPE MSR to disable
all MTRRs. All other bits in the MTRRs are undefined. Prior to initializing the MTRRs, soft-
ware (normally the system BIOS) must initialize all fixed-range and variable-range MTRR
registers fields to 0. Software can then initialize the MTRRs according to the types of memory
known to it, including memory on devices that it auto-configures. This initialization is expected
to occur prior to booting the operating system.
See Section 10.11.8, “MTRR Considerations in MP Systems,” for information on initializing
MTRRs in MP (multiple-processor) systems.
10.11.6 Remapping Memory Types
A system designer may re-map memory types to tune performance or because a future processor
may not implement all memory types supported by the Pentium 4, Intel Xeon, and P6 family
processors. The following rules support coherent memory-type re-mappings:
1. A memory type should not be mapped into another memory type that has a weaker
memory ordering model. For example, the uncacheable type cannot be mapped into any
other type, and the write-back, write-through, and write-protected types cannot be mapped
into the weakly ordered write-combining type.
2. A memory type that does not delay writes should not be mapped into a memory type that
does delay writes, because applications of such a memory type may rely on its write-
through behavior. Accordingly, the write-back type cannot be mapped into the write-
through type.
3. A memory type that views write data as not necessarily stored and read back by a
subsequent read, such as the write-protected type, can only be mapped to another type with
the same behaviour (and there are no others for the Pentium 4, Intel Xeon, and P6 family
processors) or to the uncacheable type.
In many specific cases, a system designer can have additional information about how a memory
type is used, allowing additional mappings. For example, write-through memory with no asso-
ciated write side effects can be mapped into write-back memory.