Intel IA-32 - Manual (Page 502)

12-4 Vol. 3A
SSE, SSE2 AND SSE3 SYSTEM PROGRAMMING
The SIMD floating-point exception mask bits (bits 7 through 12), the flush-to-zero flag (bit 15),
the denormals-are-zero flag (bit 6), and the rounding control field (bits 13 and 14) in the
MXCSR register should be left in their default values of 0. This permits the application to deter-
mine how these features are to be used.
12.1.5 Providing Non-Numeric Exception Handlers for
Exceptions Generated by the SSE/SSE2/SSE3 Instructions
SSE/SSE2/SSE3 instructions can generate the same type of memory access exceptions (such as,
page fault, segment not present, and limit violations) and other non-numeric exceptions as other
IA-32 architecture instructions generate.
Ordinarily, existing exception handlers can handle these and other non-numeric exceptions
without code modification. However, depending on the mechanisms used in existing exception
handlers, some modifications might need to be made.
The SSE/SSE2/SSE3 extensions can generate the non-numeric exceptions listed below:
•
Memory Access Exceptions:
— Invalid opcode (#UD).
— Stack-segment fault (#SS).
— General protection (#GP). Executing most SSE/SSE2/SSE3 instructions with an
unaligned 128-bit memory reference generates a general-protection exception. (The
MOVUPS and MOVUPD instructions allow unaligned a loads or stores of 128-bit
memory locations, without generating a general-protection exception.) A 128-bit
reference within the stack segment that is not aligned to a 16-byte boundary will also
generate a general-protection exception, instead a stack-segment fault exception
(#SS).
— Page fault (#PF).
— Alignment check (#AC). When enabled, this type of alignment check operates on
operands that are less than 128-bits in size: 16-bit, 32-bit, and 64-bit. To enable the
generation of alignment check exceptions, do the following:
• Set the AM flag (bit 18 of control register CR0)
• Set the AC flag (bit 18 of the EFLAGS register)
• CPL must be 3.
If alignment check exceptions are enabled, 16-bit, 32-bit, and 64-bit misalignment will
be detected for the MOVUPD and MOVUPS instructions; detection of 128-bit
misalignment is not guaranteed and may vary with implementation.