Intel IA-32 - Manual (Page 338)

8-14 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
8.4.7.3 Local APIC State After an INIT Reset (“Wait-for-SIPI” State)
An INIT reset of the processor can be initiated in either of two ways:
•
By asserting the processor’s INIT# pin.
•
By sending the processor an INIT IPI (an IPI with the delivery mode set to INIT).
Upon receiving an INIT through either of these mechanisms, the processor responds by begin-
ning the initialization process of the processor core and the local APIC. The state of the local
APIC following an INIT reset is the same as it is after a power-up or hardware RESET, except
that the APIC ID and arbitration ID registers are not affected. This state is also referred to at the
“wait-for-SIPI” state (see also: Section 7.5.2, “MP Initialization Protocol Requirements and
Restrictions for Intel Xeon Processors”).
8.4.7.4 Local APIC State After It Receives an INIT-Deassert IPI
Only the Pentium and P6 family processors support the INIT-deassert IPI. An INIT-disassert IPI
has no affect on the state of the APIC, other than to reload the arbitration ID register with the
value in the APIC ID register.
8.4.8 Local APIC Version Register
The local APIC contains a hardwired version register. Software can use this register to identify
the APIC version (see Figure 8-7). In addition, the register specifies the number of entries in the
local vector table (LVT) for a specific implementation.
The fields in the local APIC version register are as follows:
Version The version numbers of the local APIC:
1XH Local APIC. For Pentium 4 and Intel Xeon proces-
sors, 14H is returned.
0XH 82489DX external APIC.
20H through FFHReserved.
Max LVT Entry Shows the number of LVT entries minus 1. For the Pentium 4 and Intel
Xeon processors (which have 6 LVT entries), the value returned in the
Max LVT field is 5; for the P6 family processors (which have 5 LVT
entries), the value returned is 4; for the Pentium processor (which has
4 LVT entries), the value returned is 3.