Intel IA-32 - Manual (Page 33)

Vol. 3A xxxiii
CONTENTS
PAGE
Table 23-1. Exit Qualification for Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
Table 23-2. Exit Qualification for Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
Table 23-3. Exit Qualification for Control-Register Accesses. . . . . . . . . . . . . . . . . . . . . . 22-7
Table 23-4. Exit Qualification for MOV DR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
Table 23-5. Exit Qualification for I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
Table 24-1. SMRAM State Save Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
Table 24-2. SMRAM State Save Map for Intel EM64T . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8
Table 24-3. Processor Register Initialization in SMM. . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12
Table 24-4. I/O Instruction Information in the SMM State Save Map . . . . . . . . . . . . . . . 26-15
Table 24-5. I/O Instruction Type Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15
Table 24-6. Auto HALT Restart Flag Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18
Table 24-7. I/O Instruction Restart Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-20
Table 24-6. Exit Qualification for SMIs That Arrive Immediately
After the Retirement of an I/O Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26
Table 24-7. Format of MSEG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30
Table 25-1. Operating Modes for Host and Guest Environments . . . . . . . . . . . . . . . . . 23-14
Table A-1. Pentium 4 and Intel Xeon Processor Performance Monitoring Events
for Non-Retirement Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Table A-2. Pentium 4 and Intel Xeon Processor Performance Monitoring Events
For At-Retirement Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
Table A-3. Model-Specific Performance Monitoring Events (For Model Encoding
3 or 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-33
Table A-4. List of Metrics Available for Front_end Tagging
(For Front_end Event Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-33
Table A-5. List of Metrics Available for Execution Tagging
(For Execution Event Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-34
Table A-6. List of Metrics Available for Replay Tagging
(For Replay Event Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-35
Table A-7. Event Mask Qualification for Logical Processors . . . . . . . . . . . . . . . . . . . . . A-36
Table A-8. Performance Monitoring Events on Intel
®
Pentium
®
M Processors . . . . . . . A-41
Table A-9. Performance Monitoring Events Modified on Intel ® Pentium ® M
Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-43
Table A-10. Events That Can Be Counted with the P6 Family Performance-
Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-44
Table A-11. Events That Can Be Counted with the Pentium Processor
Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-59
Table B-1. MSRs in the Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . . . . . . . . . B-1
Table B-2. MSRs Unique to 64-bit Intel Xeon Processor MP with
Up to an 8 MB L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
Table B-3. MSRs in Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
Table B-4. MSRs in the P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47
Table B-5. MSRs in the Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-56
Table B-6. IA-32 Architectural MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-57
Table C-1. Boot Phase IPI Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Table E-1. Incremental Decoding Information: Processor Family 06H
Machine Error Codes For Machine Check . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
Table E-2. Incremental Decoding Information: Processor Family 0FH
Machine Error Codes For Machine Check . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4
Table E-3. Decoding Family 0FH Machine Check Codes for Memory
Hierarchy Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
Table F-1. EOI Message (14 Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
Table F-2. Short Message (21 Cycles). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-2