Intel IA-32 - Manual (Page 360)

8-36 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
3. If the local APIC determines that it is the designated destination for the interrupt but the
interrupt request is not one of the interrupts given in step 2, the local APIC looks for an
open slot in one of its two pending interrupt queues contained in the IRR and ISR registers
(see Figure 8-20). If a slot is available (see Section 8.8.4, “Interrupt Acceptance for Fixed
Interrupts”), places the interrupt in the slot. If a slot is not available, it rejects the interrupt
request and sends it back to the sender with a retry message.
4. When interrupts are pending in the IRR and ISR register, the local APIC dispatches them
to the processor one at a time, based on their priority and the current task and processor
priorities in the TPR and PPR (see Section 8.8.3.1, “Task and Processor Priorities”).
5. When a fixed interrupt has been dispatched to the processor core for handling, the
completion of the handler routine is indicated with an instruction in the instruction handler
code that writes to the end-of-interrupt (EOI) register in the local APIC (see Section 8.8.5,
“Signaling Interrupt Servicing Completion”). The act of writing to the EOI register causes
the local APIC to delete the interrupt from its queue and (for level-triggered interrupts)
send a message on the bus indicating that the interrupt handling has been completed. (A
write to the EOI register must not be included in the handler routine for an NMI, SMI,
INIT, ExtINT, or SIPI.)
The following sections describe the acceptance of interrupts and their handling by the local
APIC and processor in greater detail.
8.8.3 Interrupt, Task, and Processor Priority
For interrupts that are delivered to the processor through the local APIC, each interrupt has an
implied priority based on its vector number. The local APIC uses this priority to determine when
to service the interrupt relative to the other activities of the processor, including the servicing of
other interrupts.
For interrupt vectors in the range of 16 to 255, the interrupt priority is determined using the
following relationship:
priority = vector / 16
Here the quotient is rounded down to the nearest integer value to determine the priority, with 1
being the lowest priority and 15 is the highest. Because vectors 0 through 31 are reserved for
dedicated uses by the IA-32 architecture, the priorities of user defined interrupts range from 2
to 15.
Each interrupt priority level (sometimes interpreted by software as an interrupt priority class)
encompasses 16 vectors. Prioritizing interrupts within a priority level is determined by the
vector number. The higher the vector number, the higher the priority within that priority level.
In determining the priority of a vector and ranking of vectors within a priority group, the vector
number is often divided into two parts, with the high 4 bits of the vector indicating its priority
and the low 4 bit indicating its ranking within the priority group.