Intel IA-32 - Manual (Page 238)

5-62 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
Note that because SIMD floating-point exceptions are precise and occur immediately, the situ-
ation does not arise where an x87 FPU instruction, a WAIT/FWAIT instruction, or another
SSE/SSE2/SSE3 instruction will catch a pending unmasked SIMD floating-point exception.
In situations where a SIMD floating-point exception occurred while the SIMD floating-point
exceptions were masked (causing the corresponding exception flag to be set) and the SIMD
floating-point exception was subsequently unmasked, then no exception is generated when the
exception is unmasked.
When SSE/SSE2/SSE3 SIMD floating-point instructions operate on packed operands (made up
of two or four sub-operands), multiple SIMD floating-point exception conditions may be
detected. If no more than one exception condition is detected for one or more sets of sub-oper-
ands, the exception flags are set for each exception condition detected. For example, an invalid
exception detected for one sub-operand will not prevent the reporting of a divide-by-zero excep-
tion for another sub-operand. However, when two or more exceptions conditions are generated
for one sub-operand, only one exception condition is reported, according to the precedences
shown in Table 5-8. This exception precedence sometimes results in the higher priority excep-
tion condition being reported and the lower priority exception conditions being ignored.
NOTES:
1. Though a QNaN this is not an exception, the handling of a QNaN operand has precedence over lower pri-
ority exceptions. For example, a QNaN divided by zero results in a QNaN, not a divide-by-zero- excep-
tion.
2. If masked, then instruction execution continues, and a lower priority exception can occur as well.
Exception Error Code
None.
Table 5-8. SIMD Floating-Point Exceptions Priority
Priority Description
1 (Highest) Invalid operation exception due to SNaN operand (or any NaN operand for maximum,
minimum, or certain compare and convert operations).
2 QNaN operand
1
.
3 Any other invalid operation exception not mentioned above or a divide-by-zero
exception
2 .
4 Denormal operand exception 2 .
5 Numeric overflow and underflow exceptions possibly in conjunction with the inexact
result exception
2 .
6 (Lowest) Inexact result exception.