Intel IA-32 - Manual (Page 621)

Vol. 3A 17-29
IA-32 ARCHITECTURE COMPATIBILITY
•
For the 82489DX, in the lowest priority delivery mode, all the target local APICs specified
by the destination field participate in the lowest priority arbitration. For the local APIC,
only those local APICs which have free interrupt slots will participate in the lowest priority
arbitration.
17.26.2 New Features Incorporated in the Local APIC for the P6
Family and Pentium Processors
The local APIC in the Pentium and P6 family processors have the following new features not
found in the 82489DX external APIC.
•
Cluster addressing is supported in logical destination mode.
•
Focus processor checking can be enabled/disabled.
•
Interrupt input signal polarity can be programmed for the LINT0 and LINT1 pins.
•
An SMI IPI is supported through the ICR and I/O redirection table.
•
An error status register is incorporated into the LVT to log and report APIC errors.
In the P6 family processors, the local APIC incorporates an additional LVT register to handle
performance monitoring counter interrupts.
17.26.3 New Features Incorporated in the Local APIC of the
Pentium 4 and Intel Xeon Processors
The local APIC in the Pentium 4 and Intel Xeon processors has the following new features not
found in the P6 family and Pentium processors and in the 82489DX.
•
The local APIC ID is extended to 8 bits.
•
An thermal sensor register is incorporated into the LVT to handle thermal sensor
interrupts.
•
The the ability to deliver lowest-priority interrupts to a focus processor is no longer
supported.
•
The flat cluster logical destination mode is not supported.
17.27. TASK SWITCHING AND TSS
This section identifies the implementation differences of task switching, additions to the TSS
and the handling of TSSs and TSS segment selectors.