Intel IA-32 - Manual (Page 202)

5-26 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
The IST mechanism provides up to seven IST pointers in the TSS. The pointers are referenced
by an interrupt-gate descriptor in the interrupt-descriptor table (IDT); see Figure 5-7. The gate
descriptor contains a 3-bit IST index field that provides an offset into the IST section of the TSS.
Using the IST mechanism, the processor loads the value pointed by an IST pointer into the RSP.
When an interrupt occurs, the new SS selector is forced to NULL and the SS selector’s RPL field
is set to the new CPL. The old SS, RSP, RFLAGS, CS, and RIP are pushed onto the new stack.
Interrupt processing then proceeds as normal. If the IST index is zero, the modified legacy stack-
switching mechanism described above is used.
5.15 EXCEPTION AND INTERRUPT REFERENCE
The following sections describe conditions which generate exceptions and interrupts. They are
arranged in the order of vector numbers. The information contained in these sections are as
follows:
•
Exception Class — Indicates whether the exception class is a fault, trap, or abort type.
Some exceptions can be either a fault or trap type, depending on when the error condition
is detected. (This section is not applicable to interrupts.)
•
Description — Gives a general description of the purpose of the exception or interrupt
type. It also describes how the processor handles the exception or interrupt.
•
Exception Error Code — Indicates whether an error code is saved for the exception. If
one is saved, the contents of the error code are described. (This section is not applicable to
interrupts.)
•
Saved Instruction Pointer — Describes which instruction the saved (or return)
instruction pointer points to. It also indicates whether the pointer can be used to restart a
faulting instruction.
•
Program State Change — Describes the effects of the exception or interrupt on the state
of the currently running program or task and the possibilities of restarting the program or
task without loss of continuity.