Intel IA-32 - Manual (Page 367)

Vol. 3A 8-43
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
8.10 APIC BUS MESSAGE PASSING MECHANISM AND
PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS)
The Pentium 4 and Intel Xeon processors pass messages among the local and I/O APICs on the
system bus, using the system bus message passing mechanism and protocol.
The P6 family and Pentium processors, pass messages among the local and I/O APICs on the
serial APIC bus, as follows. Because only one message can be sent at a time on the APIC bus,
the I/O APIC and local APICs employ a “rotating priority” arbitration protocol to gain permis-
sion to send a message on the APIC bus. One or more APICs may start sending their messages
simultaneously. At the beginning of every message, each APIC presents the type of the message
it is sending and its current arbitration priority on the APIC bus. This information is used for
arbitration. After each arbitration cycle (within an arbitration round), only the potential winners
keep driving the bus. By the time all arbitration cycles are completed, there will be only one
APIC left driving the bus. Once a winner is selected, it is granted exclusive use of the bus, and
will continue driving the bus to send its actual message.
After each successfully transmitted message, all APICs increase their arbitration priority by 1.
The previous winner (that is, the one that has just successfully transmitted its message) assumes
a priority of 0 (lowest). An agent whose arbitration priority was 15 (highest) during arbitration,
but did not send a message, adopts the previous winner’s arbitration priority, increments by 1.
Note that the arbitration protocol described above is slightly different if one of the APICs issues
a special End-Of-Interrupt (EOI). This high-priority message is granted the bus regardless of its
sender’s arbitration priority, unless more than one APIC issues an EOI message simultaneously.
In the latter case, the APICs sending the EOI messages arbitrate using their arbitration priorities.
If the APICs are set up to use “lowest priority” arbitration (see Section 8.6.2.4, “Lowest Priority
Delivery Mode”) and multiple APICs are currently executing at the lowest priority (the value in
the APR register), the arbitration priorities (unique values in the Arb ID register) are used to
break ties. All 8 bits of the APR are used for the lowest priority arbitration.
8.10.1 Bus Message Formats
See Appendix F, “APIC Bus Message Formats,” for a description of bus message formats used
to transmit messages on the serial APIC bus.
8.11 MESSAGE SIGNALLED INTERRUPTS
The PCI Local Bus Specification, Rev 2.2 (www.pcisig.com) introduces the concept of message
signalled interrupts. Intel processors and chipsets with this capability currently include the
Pentium 4 and Intel Xeon processors. As the specification indicates:
“Message signalled interrupts (MSI) is an optional feature that enables PCI
devices to request service by writing a system-specified message to a system-
specified address (PCI DWORD memory write transaction). The transaction
address specifies the message destination while the transaction data specifies
the message. System software is expected to initialize the message