Intel IA-32 - Manual (Page 423)

Vol. 3A 9-49
PROCESSOR MANAGEMENT AND INITIALIZATION
9.11.8 Pentium 4, Intel Xeon, and P6 Family Processor
Microcode Update Specifications
This section describes the interface that an application can use to dynamically integrate
processor-specific updates into the system BIOS. In this discussion, the application is referred
to as the calling program or caller.
The real mode INT15 call specification described here is an Intel extension to an OEM BIOS.
This extension allows an application to read and modify the contents of the microcode update
data in NVRAM. The update loader, which is part of the system BIOS, cannot be updated by the
interface. All of the functions defined in the specification must be implemented for a system to
be considered compliant with the specification. The INT15 functions are accessible only from
real mode.
9.11.8.1 Responsibilities of the BIOS
If a BIOS passes the presence test (INT 15H, AX = 0D042H, BL = 0H), it must implement all
of the sub-functions defined in the INT 15H, AX = 0D042H specification. There are no optional
functions. BIOS must load the appropriate update for each processor during system initialization.
A Header Version of an update block containing the value 0FFFFFFFFH indicates that the
update block is unused and available for storing a new update.
The BIOS is responsible for providing a region of non-volatile storage (NVRAM) for each
potential processor stepping within a system. This storage unit consists of one or more update
blocks. An update block is a contiguous 2048-byte block of memory. The BIOS for a single
processor system need only provide update blocks to store one microcode update. If the BIOS
for a multiple processor system is intended to support mixed processor steppings, then the BIOS
needs to provide enough update blocks to store each unique microcode update or for each
processor socket on the OEM’s system board.
The BIOS is responsible for managing the NVRAM update blocks. This includes garbage
collection, such as removing microcode updates that exist in NVRAM for which a corre-
sponding processor does not exist in the system. This specification only provides the mechanism
for ensuring security, the uniqueness of an entry, and that stale entries are not loaded. The actual
update block management is implementation specific on a per-BIOS basis.
As an example, the BIOS may use update blocks sequentially in ascending order with CPU
signatures sorted versus the first available block. In addition, garbage collection may be imple-
mented as a setup option to clear all NVRAM slots or as BIOS code that searches and eliminates
unused entries during boot.
NOTES
For IA-32 processors starting with family 0FH and model 03H, the
microcode update may be as large as 16 KBytes. Thus, BIOS must allocate 8